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<h1><a name="Message">Timing Messages</a></h1>
<table class="summary_table">
<tr>
<td class="label">Report Title</td>
<td>Timing Analysis Report</td>
</tr>
<tr>
<td class="label">Design File</td>
<td>/home/pc/work/Tang/25K/HUB75E/HUB75E/impl/gwsynthesis/HUB75E.vg</td>
</tr>
<tr>
<td class="label">Physical Constraints File</td>
<td>/home/pc/work/Tang/25K/HUB75E/HUB75E/src/HUB75E.cst</td>
</tr>
<tr>
<td class="label">Timing Constraint File</td>
<td>---</td>
</tr>
<tr>
<td class="label">Version</td>
<td>V1.9.9 Beta-5</td>
</tr>
<tr>
<td class="label">Part Number</td>
<td>GW5A-LV25MG121NES</td>
</tr>
<tr>
<td class="label">Device</td>
<td>GW5A-25</td>
</tr>
<tr>
<td class="label">Device Version</td>
<td>A</td>
</tr>
<tr>
<td class="label">Created Time</td>
<td>Sun Oct 29 21:40:30 2023
</td>
</tr>
<tr>
<td class="label">Legal Announcement</td>
<td>Copyright (C)2014-2023 Gowin Semiconductor Corporation. All rights reserved.</td>
</tr>
</table>
<h1><a name="Summary">Timing Summaries</a></h1>
<h2><a name="STA_Tool_Run_Summary">STA Tool Run Summary:</a></h2>
<table class="summary_table">
<tr>
<td class="label">Setup Delay Model</td>
<td>Slow 0.85V -40C ES</td>
</tr>
<tr>
<td class="label">Hold Delay Model</td>
<td>Fast 0.95V 100C ES</td>
</tr>
<tr>
<td class="label">Numbers of Paths Analyzed</td>
<td>204</td>
</tr>
<tr>
<td class="label">Numbers of Endpoints Analyzed</td>
<td>172</td>
</tr>
<tr>
<td class="label">Numbers of Falling Endpoints</td>
<td>25</td>
</tr>
<tr>
<td class="label">Numbers of Setup Violated Endpoints</td>
<td>8</td>
</tr>
<tr>
<td class="label">Numbers of Hold Violated Endpoints</td>
<td>1</td>
</tr>
</table>
<h2><a name="Clock_Report">Clock Summary:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Clock Name</th>
<th class="label">Type</th>
<th class="label">Period</th>
<th class="label">Frequency(MHz)</th>
<th class="label">Rise</th>
<th class="label">Fall</th>
<th class="label">Source</th>
<th class="label">Master</th>
<th class="label">Objects</th>
</tr>
<tr>
<td>CLK_IN</td>
<td>Base</td>
<td>10.000</td>
<td>100.000
<td>0.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td>CLK_IN_ibuf/I </td>
</tr>
<tr>
<td>frame_clk_Z</td>
<td>Base</td>
<td>10.000</td>
<td>100.000
<td>0.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td>hubif/frame_clk_s1/Q </td>
</tr>
<tr>
<td>clkn[0]</td>
<td>Base</td>
<td>10.000</td>
<td>100.000
<td>0.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td>clkn_0_s0/Q </td>
</tr>
</table>
<h2><a name="Max_Frequency_Report">Max Frequency Summary:</a></h2>
<table>
<tr>
<th>NO.</th>
<th>Clock Name</th>
<th>Constraint</th>
<th>Actual Fmax</th>
<th>Logic Level</th>
<th>Entity</th>
</tr>
<tr>
<td>1</td>
<td>CLK_IN</td>
<td>100.000(MHz)</td>
<td>213.476(MHz)</td>
<td>2</td>
<td>TOP</td>
</tr>
<tr>
<td>2</td>
<td>frame_clk_Z</td>
<td>100.000(MHz)</td>
<td>432.666(MHz)</td>
<td>4</td>
<td>TOP</td>
</tr>
<tr>
<td>3</td>
<td>clkn[0]</td>
<td>100.000(MHz)</td>
<td>118.169(MHz)</td>
<td>1</td>
<td>TOP</td>
</tr>
</table>
<h2><a name="Total_Negative_Slack_Report">Total Negative Slack Summary:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Clock Name</th>
<th class="label">Analysis Type</th>
<th class="label">Endpoints TNS</th>
<th class="label">Number of Endpoints</th>
</tr>
<tr>
<td>CLK_IN</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>CLK_IN</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>frame_clk_Z</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>frame_clk_Z</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>clkn[0]</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>clkn[0]</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
</table>
<h1><a name="Detail">Timing Details</a></h1>
<h2><a name="All_Path_Slack_Table">Path Slacks Table:</a></h2>
<h3><a name="Setup_Slack_Table">Setup Paths Table</a></h3>
<h4>Report Command:report_timing -setup -max_paths 25 -max_common_paths 1</h4>
<table class="detail_table">
<tr>
<th class="label">Path Number</th>
<th class="label">Path Slack</th>
<th class="label">From Node</th>
<th class="label">To Node</th>
<th class="label">From Clock</th>
<th class="label">To Clock</th>
<th class="label">Relation</th>
<th class="label">Clock Skew</th>
<th class="label">Data Delay</th>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>1</td>
<td>-2.322</td>
<td>uresetn_s0/Q</td>
<td>hubif/hub_oe_s1/CE</td>
<td>CLK_IN:[R]</td>
<td>clkn[0]:[F]</td>
<td>5.000</td>
<td>-0.514</td>
<td>7.545</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>2</td>
<td>-1.282</td>
<td>uresetn_s0/Q</td>
<td>hubif/hub_addr_2_s1/CE</td>
<td>CLK_IN:[R]</td>
<td>clkn[0]:[F]</td>
<td>5.000</td>
<td>-0.502</td>
<td>6.492</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>3</td>
<td>-0.778</td>
<td>uresetn_s0/Q</td>
<td>hubif/hub_addr_10_s1/CE</td>
<td>CLK_IN:[R]</td>
<td>clkn[0]:[F]</td>
<td>5.000</td>
<td>-0.464</td>
<td>5.951</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>4</td>
<td>-0.587</td>
<td>uresetn_s0/Q</td>
<td>hubif/hub_addr_3_s1/CE</td>
<td>CLK_IN:[R]</td>
<td>clkn[0]:[F]</td>
<td>5.000</td>
<td>-0.462</td>
<td>5.759</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>5</td>
<td>-0.587</td>
<td>uresetn_s0/Q</td>
<td>hubif/hub_addr_4_s1/CE</td>
<td>CLK_IN:[R]</td>
<td>clkn[0]:[F]</td>
<td>5.000</td>
<td>-0.462</td>
<td>5.759</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>6</td>
<td>-0.587</td>
<td>uresetn_s0/Q</td>
<td>hubif/hub_addr_7_s1/CE</td>
<td>CLK_IN:[R]</td>
<td>clkn[0]:[F]</td>
<td>5.000</td>
<td>-0.462</td>
<td>5.759</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>7</td>
<td>-0.587</td>
<td>uresetn_s0/Q</td>
<td>hubif/hub_addr_9_s1/CE</td>
<td>CLK_IN:[R]</td>
<td>clkn[0]:[F]</td>
<td>5.000</td>
<td>-0.462</td>
<td>5.759</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>8</td>
<td>-0.516</td>
<td>uresetn_s0/Q</td>
<td>hubif/hub_addr_5_s1/CE</td>
<td>CLK_IN:[R]</td>
<td>clkn[0]:[F]</td>
<td>5.000</td>
<td>-0.472</td>
<td>5.696</td>
</tr>
<tr>
<td>9</td>
<td>0.624</td>
<td>uresetn_s0/Q</td>
<td>hubif/frame_clk_s1/CE</td>
<td>CLK_IN:[R]</td>
<td>clkn[0]:[F]</td>
<td>5.000</td>
<td>-0.499</td>
<td>4.584</td>
</tr>
<tr>
<td>10</td>
<td>0.963</td>
<td>uresetn_s0/Q</td>
<td>hubif/hub_addr_0_s3/D</td>
<td>CLK_IN:[R]</td>
<td>clkn[0]:[F]</td>
<td>5.000</td>
<td>-0.499</td>
<td>4.493</td>
</tr>
<tr>
<td>11</td>
<td>0.963</td>
<td>uresetn_s0/Q</td>
<td>hubif/hub_addr_1_s3/D</td>
<td>CLK_IN:[R]</td>
<td>clkn[0]:[F]</td>
<td>5.000</td>
<td>-0.499</td>
<td>4.493</td>
</tr>
<tr>
<td>12</td>
<td>0.963</td>
<td>uresetn_s0/Q</td>
<td>hubif/hub_addr_6_s3/D</td>
<td>CLK_IN:[R]</td>
<td>clkn[0]:[F]</td>
<td>5.000</td>
<td>-0.499</td>
<td>4.493</td>
</tr>
<tr>
<td>13</td>
<td>0.963</td>
<td>uresetn_s0/Q</td>
<td>hubif/hub_addr_8_s3/D</td>
<td>CLK_IN:[R]</td>
<td>clkn[0]:[F]</td>
<td>5.000</td>
<td>-0.499</td>
<td>4.493</td>
</tr>
<tr>
<td>14</td>
<td>0.769</td>
<td>hubif/hub_addr_1_s3/Q</td>
<td>logo_rom/prom_inst_2/AD[4]</td>
<td>clkn[0]:[F]</td>
<td>clkn[0]:[R]</td>
<td>5.000</td>
<td>-0.112</td>
<td>4.309</td>
</tr>
<tr>
<td>15</td>
<td>0.870</td>
<td>hubif/hub_addr_8_s3/Q</td>
<td>logo_rom/prom_inst_2/AD[11]</td>
<td>clkn[0]:[F]</td>
<td>clkn[0]:[R]</td>
<td>5.000</td>
<td>-0.112</td>
<td>4.207</td>
</tr>
<tr>
<td>16</td>
<td>1.239</td>
<td>hubif/hub_addr_3_s1/Q</td>
<td>logo_rom/prom_inst_2/AD[6]</td>
<td>clkn[0]:[F]</td>
<td>clkn[0]:[R]</td>
<td>5.000</td>
<td>-0.148</td>
<td>3.875</td>
</tr>
<tr>
<td>17</td>
<td>1.264</td>
<td>hubif/hub_addr_1_s3/Q</td>
<td>logo_rom/prom_inst_1/AD[4]</td>
<td>clkn[0]:[F]</td>
<td>clkn[0]:[R]</td>
<td>5.000</td>
<td>-0.112</td>
<td>3.814</td>
</tr>
<tr>
<td>18</td>
<td>1.294</td>
<td>hubif/hub_addr_9_s1/Q</td>
<td>logo_rom/prom_inst_2/AD[12]</td>
<td>clkn[0]:[F]</td>
<td>clkn[0]:[R]</td>
<td>5.000</td>
<td>-0.148</td>
<td>3.820</td>
</tr>
<tr>
<td>19</td>
<td>1.333</td>
<td>hubif/hub_addr_10_s1/Q</td>
<td>logo_rom/prom_inst_2/AD[13]</td>
<td>clkn[0]:[F]</td>
<td>clkn[0]:[R]</td>
<td>5.000</td>
<td>-0.147</td>
<td>3.779</td>
</tr>
<tr>
<td>20</td>
<td>1.484</td>
<td>hubif/hub_addr_7_s1/Q</td>
<td>logo_rom/prom_inst_2/AD[10]</td>
<td>clkn[0]:[F]</td>
<td>clkn[0]:[R]</td>
<td>5.000</td>
<td>-0.148</td>
<td>3.630</td>
</tr>
<tr>
<td>21</td>
<td>1.819</td>
<td>hubif/hub_addr_6_s3/Q</td>
<td>logo_rom/prom_inst_3/AD[9]</td>
<td>clkn[0]:[F]</td>
<td>clkn[0]:[R]</td>
<td>5.000</td>
<td>-0.103</td>
<td>3.249</td>
</tr>
<tr>
<td>22</td>
<td>1.867</td>
<td>hubif/hub_addr_8_s3/Q</td>
<td>logo_rom/prom_inst_3/AD[11]</td>
<td>clkn[0]:[F]</td>
<td>clkn[0]:[R]</td>
<td>5.000</td>
<td>-0.103</td>
<td>3.201</td>
</tr>
<tr>
<td>23</td>
<td>2.066</td>
<td>hubif/hub_addr_8_s3/Q</td>
<td>logo_rom/prom_inst_1/AD[11]</td>
<td>clkn[0]:[F]</td>
<td>clkn[0]:[R]</td>
<td>5.000</td>
<td>-0.112</td>
<td>3.011</td>
</tr>
<tr>
<td>24</td>
<td>2.117</td>
<td>hubif/hub_addr_2_s1/Q</td>
<td>logo_rom/prom_inst_3/AD[5]</td>
<td>clkn[0]:[F]</td>
<td>clkn[0]:[R]</td>
<td>5.000</td>
<td>-0.100</td>
<td>2.949</td>
</tr>
<tr>
<td>25</td>
<td>2.209</td>
<td>hubif/hub_addr_6_s3/Q</td>
<td>logo_rom/prom_inst_1/AD[9]</td>
<td>clkn[0]:[F]</td>
<td>clkn[0]:[R]</td>
<td>5.000</td>
<td>-0.112</td>
<td>2.869</td>
</tr>
</table>
<h3><a name="Hold_Slack_Table">Hold Paths Table</a></h3>
<h4>Report Command:report_timing -hold -max_paths 25 -max_common_paths 1</h4>
<table class="detail_table">
<tr>
<th class="label">Path Number</th>
<th class="label">Path Slack</th>
<th class="label">From Node</th>
<th class="label">To Node</th>
<th class="label">From Clock</th>
<th class="label">To Clock</th>
<th class="label">Relation</th>
<th class="label">Clock Skew</th>
<th class="label">Data Delay</th>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>1</td>
<td>-0.909</td>
<td>hubif/n51_s2/I0</td>
<td>clkn_0_s0/D</td>
<td>clkn[0]:[R]</td>
<td>CLK_IN:[R]</td>
<td>0.000</td>
<td>-1.072</td>
<td>0.199</td>
</tr>
<tr>
<td>2</td>
<td>0.339</td>
<td>hubif/hub_addr_1_s3/Q</td>
<td>hubif/hub_addr_1_s3/D</td>
<td>clkn[0]:[F]</td>
<td>clkn[0]:[F]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.394</td>
</tr>
<tr>
<td>3</td>
<td>0.339</td>
<td>hubif/hub_addr_8_s3/Q</td>
<td>hubif/hub_addr_8_s3/D</td>
<td>clkn[0]:[F]</td>
<td>clkn[0]:[F]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.394</td>
</tr>
<tr>
<td>4</td>
<td>0.343</td>
<td>hubif/state_1_s5/Q</td>
<td>hubif/state_1_s5/D</td>
<td>clkn[0]:[F]</td>
<td>clkn[0]:[F]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.398</td>
</tr>
<tr>
<td>5</td>
<td>0.343</td>
<td>hubif/hub_addr_7_s1/Q</td>
<td>hubif/hub_addr_7_s1/D</td>
<td>clkn[0]:[F]</td>
<td>clkn[0]:[F]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.398</td>
</tr>
<tr>
<td>6</td>
<td>0.346</td>
<td>hubif/state_0_s3/Q</td>
<td>hubif/state_0_s3/D</td>
<td>clkn[0]:[F]</td>
<td>clkn[0]:[F]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.401</td>
</tr>
<tr>
<td>7</td>
<td>0.374</td>
<td>frame_count_0_s0/Q</td>
<td>frame_count_0_s0/D</td>
<td>frame_clk_Z:[R]</td>
<td>frame_clk_Z:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.375</td>
</tr>
<tr>
<td>8</td>
<td>0.413</td>
<td>hubif/hub_addr_2_s1/Q</td>
<td>hubif/hub_addr_2_s1/D</td>
<td>clkn[0]:[F]</td>
<td>clkn[0]:[F]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.467</td>
</tr>
<tr>
<td>9</td>
<td>0.413</td>
<td>hubif/hub_addr_4_s1/Q</td>
<td>hubif/hub_addr_4_s1/D</td>
<td>clkn[0]:[F]</td>
<td>clkn[0]:[F]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.467</td>
</tr>
<tr>
<td>10</td>
<td>0.458</td>
<td>hubif/hub_addr_9_s1/Q</td>
<td>hubif/hub_addr_9_s1/D</td>
<td>clkn[0]:[F]</td>
<td>clkn[0]:[F]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.512</td>
</tr>
<tr>
<td>11</td>
<td>0.461</td>
<td>hubif/hub_addr_0_s3/Q</td>
<td>hubif/hub_addr_0_s3/D</td>
<td>clkn[0]:[F]</td>
<td>clkn[0]:[F]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.516</td>
</tr>
<tr>
<td>12</td>
<td>0.461</td>
<td>hubif/hub_addr_6_s3/Q</td>
<td>hubif/hub_addr_6_s3/D</td>
<td>clkn[0]:[F]</td>
<td>clkn[0]:[F]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.516</td>
</tr>
<tr>
<td>13</td>
<td>0.461</td>
<td>hubif/hub_addr_10_s1/Q</td>
<td>hubif/hub_addr_10_s1/D</td>
<td>clkn[0]:[F]</td>
<td>clkn[0]:[F]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.516</td>
</tr>
<tr>
<td>14</td>
<td>0.529</td>
<td>frame_count_3_s0/Q</td>
<td>frame_count_3_s0/D</td>
<td>frame_clk_Z:[R]</td>
<td>frame_clk_Z:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.505</td>
</tr>
<tr>
<td>15</td>
<td>0.532</td>
<td>reset_cnt_2_s0/Q</td>
<td>reset_cnt_2_s0/D</td>
<td>CLK_IN:[R]</td>
<td>CLK_IN:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.509</td>
</tr>
<tr>
<td>16</td>
<td>0.539</td>
<td>hubif/hub_addr_4_s1/Q</td>
<td>hubif/hub_addr_5_s1/D</td>
<td>clkn[0]:[F]</td>
<td>clkn[0]:[F]</td>
<td>0.000</td>
<td>-0.005</td>
<td>0.575</td>
</tr>
<tr>
<td>17</td>
<td>0.540</td>
<td>frame_count_7_s0/Q</td>
<td>frame_count_7_s0/D</td>
<td>frame_clk_Z:[R]</td>
<td>frame_clk_Z:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.516</td>
</tr>
<tr>
<td>18</td>
<td>0.540</td>
<td>frame_count_9_s0/Q</td>
<td>frame_count_9_s0/D</td>
<td>frame_clk_Z:[R]</td>
<td>frame_clk_Z:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.516</td>
</tr>
<tr>
<td>19</td>
<td>0.540</td>
<td>hubif/hub_addr_3_s1/Q</td>
<td>hubif/hub_addr_3_s1/D</td>
<td>clkn[0]:[F]</td>
<td>clkn[0]:[F]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.595</td>
</tr>
<tr>
<td>20</td>
<td>0.567</td>
<td>frame_count_1_s0/Q</td>
<td>frame_count_1_s0/D</td>
<td>frame_clk_Z:[R]</td>
<td>frame_clk_Z:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.569</td>
</tr>
<tr>
<td>21</td>
<td>0.579</td>
<td>frame_count_3_s0/Q</td>
<td>frame_count_5_s0/D</td>
<td>frame_clk_Z:[R]</td>
<td>frame_clk_Z:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.580</td>
</tr>
<tr>
<td>22</td>
<td>0.582</td>
<td>reset_cnt_2_s0/Q</td>
<td>reset_cnt_4_s0/D</td>
<td>CLK_IN:[R]</td>
<td>CLK_IN:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.584</td>
</tr>
<tr>
<td>23</td>
<td>0.585</td>
<td>frame_count_3_s0/Q</td>
<td>frame_count_4_s0/D</td>
<td>frame_clk_Z:[R]</td>
<td>frame_clk_Z:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.586</td>
</tr>
<tr>
<td>24</td>
<td>0.589</td>
<td>reset_cnt_2_s0/Q</td>
<td>reset_cnt_3_s0/D</td>
<td>CLK_IN:[R]</td>
<td>CLK_IN:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.590</td>
</tr>
<tr>
<td>25</td>
<td>0.596</td>
<td>frame_count_7_s0/Q</td>
<td>frame_count_8_s0/D</td>
<td>frame_clk_Z:[R]</td>
<td>frame_clk_Z:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.597</td>
</tr>
</table>
<h3><a name="Recovery_Slack_Table">Recovery Paths Table</a></h3>
<h4>Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1</h4>
<h4>Nothing to report!</h4>
<h3><a name="Removal_Slack_Table">Removal Paths Table</a></h3>
<h4>Report Command:report_timing -removal -max_paths 25 -max_common_paths 1</h4>
<h4>Nothing to report!</h4>
<h2><a name="MIN_PULSE_WIDTH_TABLE">Minimum Pulse Width Table:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Number</th>
<th class="label">Slack</th>
<th class="label">Actual Width</th>
<th class="label">Required Width</th>
<th class="label">Type</th>
<th class="label">Clock</th>
<th class="label">Objects</th>
</tr>
<h4>Report Command:report_min_pulse_width -nworst 10 -detail</h4>
<tr>
<td>1</td>
<td>3.042</td>
<td>4.042</td>
<td>1.000</td>
<td>High Pulse Width</td>
<td>clkn[0]</td>
<td>logo_rom/prom_inst_1</td>
</tr>
<tr>
<td>2</td>
<td>3.042</td>
<td>4.042</td>
<td>1.000</td>
<td>High Pulse Width</td>
<td>clkn[0]</td>
<td>logo_rom/prom_inst_2</td>
</tr>
<tr>
<td>3</td>
<td>3.047</td>
<td>4.047</td>
<td>1.000</td>
<td>High Pulse Width</td>
<td>clkn[0]</td>
<td>logo_rom/prom_inst_0</td>
</tr>
<tr>
<td>4</td>
<td>3.047</td>
<td>4.047</td>
<td>1.000</td>
<td>High Pulse Width</td>
<td>clkn[0]</td>
<td>logo_rom/prom_inst_3</td>
</tr>
<tr>
<td>5</td>
<td>3.100</td>
<td>4.100</td>
<td>1.000</td>
<td>Low Pulse Width</td>
<td>clkn[0]</td>
<td>logo_rom/prom_inst_1</td>
</tr>
<tr>
<td>6</td>
<td>3.100</td>
<td>4.100</td>
<td>1.000</td>
<td>Low Pulse Width</td>
<td>clkn[0]</td>
<td>logo_rom/prom_inst_2</td>
</tr>
<tr>
<td>7</td>
<td>3.105</td>
<td>4.105</td>
<td>1.000</td>
<td>Low Pulse Width</td>
<td>clkn[0]</td>
<td>logo_rom/prom_inst_3</td>
</tr>
<tr>
<td>8</td>
<td>3.105</td>
<td>4.105</td>
<td>1.000</td>
<td>Low Pulse Width</td>
<td>clkn[0]</td>
<td>logo_rom/prom_inst_0</td>
</tr>
<tr>
<td>9</td>
<td>3.751</td>
<td>4.001</td>
<td>0.250</td>
<td>High Pulse Width</td>
<td>frame_clk_Z</td>
<td>frame_count_0_s0</td>
</tr>
<tr>
<td>10</td>
<td>3.756</td>
<td>4.006</td>
<td>0.250</td>
<td>High Pulse Width</td>
<td>frame_clk_Z</td>
<td>frame_count_5_s0</td>
</tr>
</table>
<h2><a name="Timing_Report_by_Analysis_Type">Timing Report By Analysis Type:</a></h2>
<h3><a name="Setup_Analysis">Setup Analysis Report</a></h3>
<h4>Report Command:report_timing -setup -max_paths 25 -max_common_paths 1</h4>
<h3>Path1</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-2.322</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>9.124</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>6.801</td>
</tr>
<tr>
<td class="label">From</td>
<td>uresetn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>hubif/hub_oe_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>CLK_IN:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clkn[0]:[F]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>CLK_IN</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>CLK_IN_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>8</td>
<td>IOB12[A]</td>
<td>CLK_IN_ibuf/O</td>
</tr>
<tr>
<td>1.579</td>
<td>0.896</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOT3[A]</td>
<td>uresetn_s0/CLK</td>
</tr>
<tr>
<td>1.961</td>
<td>0.382</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>IOT3[A]</td>
<td style=" font-weight:bold;">uresetn_s0/Q</td>
</tr>
<tr>
<td>5.120</td>
<td>3.159</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C46[3][A]</td>
<td>n106_s1/I2</td>
</tr>
<tr>
<td>5.385</td>
<td>0.265</td>
<td>tINS</td>
<td>RR</td>
<td>22</td>
<td>R21C46[3][A]</td>
<td style=" background: #97FFFF;">n106_s1/F</td>
</tr>
<tr>
<td>6.609</td>
<td>1.224</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C45[0][A]</td>
<td>hubif/hub_oe_s3/I1</td>
</tr>
<tr>
<td>6.871</td>
<td>0.262</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R17C45[0][A]</td>
<td style=" background: #97FFFF;">hubif/hub_oe_s3/F</td>
</tr>
<tr>
<td>9.124</td>
<td>2.253</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOT63[B]</td>
<td style=" font-weight:bold;">hubif/hub_oe_s1/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clkn[0]</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>22</td>
<td>R21C44[0][A]</td>
<td>clkn_0_s0/Q</td>
</tr>
<tr>
<td>7.092</td>
<td>2.092</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>IOT63[B]</td>
<td>hubif/hub_oe_s1/CLK</td>
</tr>
<tr>
<td>7.057</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>hubif/hub_oe_s1</td>
</tr>
<tr>
<td>6.801</td>
<td>-0.256</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>IOT63[B]</td>
<td>hubif/hub_oe_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.514</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>3</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 43.230%; route: 0.896, 56.770%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.527, 6.991%; route: 6.635, 87.939%; tC2Q: 0.382, 5.070%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.092, 100.000%</td>
</tr>
</table>
<h3>Path2</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-1.282</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>8.071</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>6.789</td>
</tr>
<tr>
<td class="label">From</td>
<td>uresetn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>hubif/hub_addr_2_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>CLK_IN:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clkn[0]:[F]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>CLK_IN</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>CLK_IN_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>8</td>
<td>IOB12[A]</td>
<td>CLK_IN_ibuf/O</td>
</tr>
<tr>
<td>1.579</td>
<td>0.896</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOT3[A]</td>
<td>uresetn_s0/CLK</td>
</tr>
<tr>
<td>1.961</td>
<td>0.382</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>IOT3[A]</td>
<td style=" font-weight:bold;">uresetn_s0/Q</td>
</tr>
<tr>
<td>5.120</td>
<td>3.159</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C46[3][A]</td>
<td>n106_s1/I2</td>
</tr>
<tr>
<td>5.385</td>
<td>0.265</td>
<td>tINS</td>
<td>RR</td>
<td>22</td>
<td>R21C46[3][A]</td>
<td style=" background: #97FFFF;">n106_s1/F</td>
</tr>
<tr>
<td>6.609</td>
<td>1.224</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C44[0][B]</td>
<td>hubif/hub_addr_10_s5/I1</td>
</tr>
<tr>
<td>7.135</td>
<td>0.526</td>
<td>tINS</td>
<td>RR</td>
<td>7</td>
<td>R17C44[0][B]</td>
<td style=" background: #97FFFF;">hubif/hub_addr_10_s5/F</td>
</tr>
<tr>
<td>8.071</td>
<td>0.936</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C45[2][A]</td>
<td style=" font-weight:bold;">hubif/hub_addr_2_s1/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clkn[0]</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>22</td>
<td>R21C44[0][A]</td>
<td>clkn_0_s0/Q</td>
</tr>
<tr>
<td>7.080</td>
<td>2.080</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R20C45[2][A]</td>
<td>hubif/hub_addr_2_s1/CLK</td>
</tr>
<tr>
<td>7.045</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>hubif/hub_addr_2_s1</td>
</tr>
<tr>
<td>6.789</td>
<td>-0.256</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R20C45[2][A]</td>
<td>hubif/hub_addr_2_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.502</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>3</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 43.230%; route: 0.896, 56.770%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.791, 12.187%; route: 5.319, 81.921%; tC2Q: 0.382, 5.891%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.080, 100.000%</td>
</tr>
</table>
<h3>Path3</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-0.778</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.530</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>6.752</td>
</tr>
<tr>
<td class="label">From</td>
<td>uresetn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>hubif/hub_addr_10_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>CLK_IN:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clkn[0]:[F]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>CLK_IN</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>CLK_IN_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>8</td>
<td>IOB12[A]</td>
<td>CLK_IN_ibuf/O</td>
</tr>
<tr>
<td>1.579</td>
<td>0.896</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOT3[A]</td>
<td>uresetn_s0/CLK</td>
</tr>
<tr>
<td>1.961</td>
<td>0.382</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>IOT3[A]</td>
<td style=" font-weight:bold;">uresetn_s0/Q</td>
</tr>
<tr>
<td>5.120</td>
<td>3.159</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C46[3][A]</td>
<td>n106_s1/I2</td>
</tr>
<tr>
<td>5.385</td>
<td>0.265</td>
<td>tINS</td>
<td>RR</td>
<td>22</td>
<td>R21C46[3][A]</td>
<td style=" background: #97FFFF;">n106_s1/F</td>
</tr>
<tr>
<td>6.609</td>
<td>1.224</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C44[0][B]</td>
<td>hubif/hub_addr_10_s5/I1</td>
</tr>
<tr>
<td>7.135</td>
<td>0.526</td>
<td>tINS</td>
<td>RR</td>
<td>7</td>
<td>R17C44[0][B]</td>
<td style=" background: #97FFFF;">hubif/hub_addr_10_s5/F</td>
</tr>
<tr>
<td>7.530</td>
<td>0.395</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C45[0][B]</td>
<td style=" font-weight:bold;">hubif/hub_addr_10_s1/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clkn[0]</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>22</td>
<td>R21C44[0][A]</td>
<td>clkn_0_s0/Q</td>
</tr>
<tr>
<td>7.043</td>
<td>2.043</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C45[0][B]</td>
<td>hubif/hub_addr_10_s1/CLK</td>
</tr>
<tr>
<td>7.008</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>hubif/hub_addr_10_s1</td>
</tr>
<tr>
<td>6.752</td>
<td>-0.256</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R18C45[0][B]</td>
<td>hubif/hub_addr_10_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.464</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>3</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 43.230%; route: 0.896, 56.770%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.791, 13.296%; route: 4.778, 80.277%; tC2Q: 0.382, 6.427%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.043, 100.000%</td>
</tr>
</table>
<h3>Path4</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-0.587</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.337</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>6.750</td>
</tr>
<tr>
<td class="label">From</td>
<td>uresetn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>hubif/hub_addr_3_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>CLK_IN:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clkn[0]:[F]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>CLK_IN</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>CLK_IN_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>8</td>
<td>IOB12[A]</td>
<td>CLK_IN_ibuf/O</td>
</tr>
<tr>
<td>1.579</td>
<td>0.896</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOT3[A]</td>
<td>uresetn_s0/CLK</td>
</tr>
<tr>
<td>1.961</td>
<td>0.382</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>IOT3[A]</td>
<td style=" font-weight:bold;">uresetn_s0/Q</td>
</tr>
<tr>
<td>5.120</td>
<td>3.159</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C46[3][A]</td>
<td>n106_s1/I2</td>
</tr>
<tr>
<td>5.385</td>
<td>0.265</td>
<td>tINS</td>
<td>RR</td>
<td>22</td>
<td>R21C46[3][A]</td>
<td style=" background: #97FFFF;">n106_s1/F</td>
</tr>
<tr>
<td>6.609</td>
<td>1.224</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C44[0][B]</td>
<td>hubif/hub_addr_10_s5/I1</td>
</tr>
<tr>
<td>7.135</td>
<td>0.526</td>
<td>tINS</td>
<td>RR</td>
<td>7</td>
<td>R17C44[0][B]</td>
<td style=" background: #97FFFF;">hubif/hub_addr_10_s5/F</td>
</tr>
<tr>
<td>7.337</td>
<td>0.203</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C45[2][B]</td>
<td style=" font-weight:bold;">hubif/hub_addr_3_s1/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clkn[0]</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>22</td>
<td>R21C44[0][A]</td>
<td>clkn_0_s0/Q</td>
</tr>
<tr>
<td>7.041</td>
<td>2.041</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C45[2][B]</td>
<td>hubif/hub_addr_3_s1/CLK</td>
</tr>
<tr>
<td>7.006</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>hubif/hub_addr_3_s1</td>
</tr>
<tr>
<td>6.750</td>
<td>-0.256</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R17C45[2][B]</td>
<td>hubif/hub_addr_3_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.462</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>3</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 43.230%; route: 0.896, 56.770%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.791, 13.740%; route: 4.585, 79.618%; tC2Q: 0.382, 6.642%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.041, 100.000%</td>
</tr>
</table>
<h3>Path5</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-0.587</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.337</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>6.750</td>
</tr>
<tr>
<td class="label">From</td>
<td>uresetn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>hubif/hub_addr_4_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>CLK_IN:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clkn[0]:[F]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>CLK_IN</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>CLK_IN_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>8</td>
<td>IOB12[A]</td>
<td>CLK_IN_ibuf/O</td>
</tr>
<tr>
<td>1.579</td>
<td>0.896</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOT3[A]</td>
<td>uresetn_s0/CLK</td>
</tr>
<tr>
<td>1.961</td>
<td>0.382</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>IOT3[A]</td>
<td style=" font-weight:bold;">uresetn_s0/Q</td>
</tr>
<tr>
<td>5.120</td>
<td>3.159</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C46[3][A]</td>
<td>n106_s1/I2</td>
</tr>
<tr>
<td>5.385</td>
<td>0.265</td>
<td>tINS</td>
<td>RR</td>
<td>22</td>
<td>R21C46[3][A]</td>
<td style=" background: #97FFFF;">n106_s1/F</td>
</tr>
<tr>
<td>6.609</td>
<td>1.224</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C44[0][B]</td>
<td>hubif/hub_addr_10_s5/I1</td>
</tr>
<tr>
<td>7.135</td>
<td>0.526</td>
<td>tINS</td>
<td>RR</td>
<td>7</td>
<td>R17C44[0][B]</td>
<td style=" background: #97FFFF;">hubif/hub_addr_10_s5/F</td>
</tr>
<tr>
<td>7.337</td>
<td>0.203</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C45[2][A]</td>
<td style=" font-weight:bold;">hubif/hub_addr_4_s1/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clkn[0]</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>22</td>
<td>R21C44[0][A]</td>
<td>clkn_0_s0/Q</td>
</tr>
<tr>
<td>7.041</td>
<td>2.041</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C45[2][A]</td>
<td>hubif/hub_addr_4_s1/CLK</td>
</tr>
<tr>
<td>7.006</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>hubif/hub_addr_4_s1</td>
</tr>
<tr>
<td>6.750</td>
<td>-0.256</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R17C45[2][A]</td>
<td>hubif/hub_addr_4_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.462</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>3</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 43.230%; route: 0.896, 56.770%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.791, 13.740%; route: 4.585, 79.618%; tC2Q: 0.382, 6.642%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.041, 100.000%</td>
</tr>
</table>
<h3>Path6</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-0.587</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.337</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>6.750</td>
</tr>
<tr>
<td class="label">From</td>
<td>uresetn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>hubif/hub_addr_7_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>CLK_IN:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clkn[0]:[F]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>CLK_IN</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>CLK_IN_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>8</td>
<td>IOB12[A]</td>
<td>CLK_IN_ibuf/O</td>
</tr>
<tr>
<td>1.579</td>
<td>0.896</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOT3[A]</td>
<td>uresetn_s0/CLK</td>
</tr>
<tr>
<td>1.961</td>
<td>0.382</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>IOT3[A]</td>
<td style=" font-weight:bold;">uresetn_s0/Q</td>
</tr>
<tr>
<td>5.120</td>
<td>3.159</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C46[3][A]</td>
<td>n106_s1/I2</td>
</tr>
<tr>
<td>5.385</td>
<td>0.265</td>
<td>tINS</td>
<td>RR</td>
<td>22</td>
<td>R21C46[3][A]</td>
<td style=" background: #97FFFF;">n106_s1/F</td>
</tr>
<tr>
<td>6.609</td>
<td>1.224</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C44[0][B]</td>
<td>hubif/hub_addr_10_s5/I1</td>
</tr>
<tr>
<td>7.135</td>
<td>0.526</td>
<td>tINS</td>
<td>RR</td>
<td>7</td>
<td>R17C44[0][B]</td>
<td style=" background: #97FFFF;">hubif/hub_addr_10_s5/F</td>
</tr>
<tr>
<td>7.337</td>
<td>0.203</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C45[1][A]</td>
<td style=" font-weight:bold;">hubif/hub_addr_7_s1/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clkn[0]</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>22</td>
<td>R21C44[0][A]</td>
<td>clkn_0_s0/Q</td>
</tr>
<tr>
<td>7.041</td>
<td>2.041</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C45[1][A]</td>
<td>hubif/hub_addr_7_s1/CLK</td>
</tr>
<tr>
<td>7.006</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>hubif/hub_addr_7_s1</td>
</tr>
<tr>
<td>6.750</td>
<td>-0.256</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R17C45[1][A]</td>
<td>hubif/hub_addr_7_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.462</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>3</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 43.230%; route: 0.896, 56.770%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.791, 13.740%; route: 4.585, 79.618%; tC2Q: 0.382, 6.642%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.041, 100.000%</td>
</tr>
</table>
<h3>Path7</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-0.587</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.337</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>6.750</td>
</tr>
<tr>
<td class="label">From</td>
<td>uresetn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>hubif/hub_addr_9_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>CLK_IN:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clkn[0]:[F]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>CLK_IN</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>CLK_IN_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>8</td>
<td>IOB12[A]</td>
<td>CLK_IN_ibuf/O</td>
</tr>
<tr>
<td>1.579</td>
<td>0.896</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOT3[A]</td>
<td>uresetn_s0/CLK</td>
</tr>
<tr>
<td>1.961</td>
<td>0.382</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>IOT3[A]</td>
<td style=" font-weight:bold;">uresetn_s0/Q</td>
</tr>
<tr>
<td>5.120</td>
<td>3.159</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C46[3][A]</td>
<td>n106_s1/I2</td>
</tr>
<tr>
<td>5.385</td>
<td>0.265</td>
<td>tINS</td>
<td>RR</td>
<td>22</td>
<td>R21C46[3][A]</td>
<td style=" background: #97FFFF;">n106_s1/F</td>
</tr>
<tr>
<td>6.609</td>
<td>1.224</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C44[0][B]</td>
<td>hubif/hub_addr_10_s5/I1</td>
</tr>
<tr>
<td>7.135</td>
<td>0.526</td>
<td>tINS</td>
<td>RR</td>
<td>7</td>
<td>R17C44[0][B]</td>
<td style=" background: #97FFFF;">hubif/hub_addr_10_s5/F</td>
</tr>
<tr>
<td>7.337</td>
<td>0.203</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C45[0][B]</td>
<td style=" font-weight:bold;">hubif/hub_addr_9_s1/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clkn[0]</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>22</td>
<td>R21C44[0][A]</td>
<td>clkn_0_s0/Q</td>
</tr>
<tr>
<td>7.041</td>
<td>2.041</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C45[0][B]</td>
<td>hubif/hub_addr_9_s1/CLK</td>
</tr>
<tr>
<td>7.006</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>hubif/hub_addr_9_s1</td>
</tr>
<tr>
<td>6.750</td>
<td>-0.256</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R17C45[0][B]</td>
<td>hubif/hub_addr_9_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.462</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>3</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 43.230%; route: 0.896, 56.770%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.791, 13.740%; route: 4.585, 79.618%; tC2Q: 0.382, 6.642%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.041, 100.000%</td>
</tr>
</table>
<h3>Path8</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-0.516</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.275</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>6.759</td>
</tr>
<tr>
<td class="label">From</td>
<td>uresetn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>hubif/hub_addr_5_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>CLK_IN:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clkn[0]:[F]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>CLK_IN</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>CLK_IN_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>8</td>
<td>IOB12[A]</td>
<td>CLK_IN_ibuf/O</td>
</tr>
<tr>
<td>1.579</td>
<td>0.896</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOT3[A]</td>
<td>uresetn_s0/CLK</td>
</tr>
<tr>
<td>1.961</td>
<td>0.382</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>IOT3[A]</td>
<td style=" font-weight:bold;">uresetn_s0/Q</td>
</tr>
<tr>
<td>5.120</td>
<td>3.159</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C46[3][A]</td>
<td>n106_s1/I2</td>
</tr>
<tr>
<td>5.385</td>
<td>0.265</td>
<td>tINS</td>
<td>RR</td>
<td>22</td>
<td>R21C46[3][A]</td>
<td style=" background: #97FFFF;">n106_s1/F</td>
</tr>
<tr>
<td>6.609</td>
<td>1.224</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C44[0][B]</td>
<td>hubif/hub_addr_10_s5/I1</td>
</tr>
<tr>
<td>7.135</td>
<td>0.526</td>
<td>tINS</td>
<td>RR</td>
<td>7</td>
<td>R17C44[0][B]</td>
<td style=" background: #97FFFF;">hubif/hub_addr_10_s5/F</td>
</tr>
<tr>
<td>7.275</td>
<td>0.140</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C44[3][A]</td>
<td style=" font-weight:bold;">hubif/hub_addr_5_s1/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clkn[0]</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>22</td>
<td>R21C44[0][A]</td>
<td>clkn_0_s0/Q</td>
</tr>
<tr>
<td>7.051</td>
<td>2.051</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C44[3][A]</td>
<td>hubif/hub_addr_5_s1/CLK</td>
</tr>
<tr>
<td>7.016</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>hubif/hub_addr_5_s1</td>
</tr>
<tr>
<td>6.759</td>
<td>-0.256</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R17C44[3][A]</td>
<td>hubif/hub_addr_5_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.472</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>3</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 43.230%; route: 0.896, 56.770%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.791, 13.891%; route: 4.523, 79.394%; tC2Q: 0.382, 6.715%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.051, 100.000%</td>
</tr>
</table>
<h3>Path9</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.624</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>6.162</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>6.786</td>
</tr>
<tr>
<td class="label">From</td>
<td>uresetn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>hubif/frame_clk_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>CLK_IN:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clkn[0]:[F]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>CLK_IN</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>CLK_IN_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>8</td>
<td>IOB12[A]</td>
<td>CLK_IN_ibuf/O</td>
</tr>
<tr>
<td>1.579</td>
<td>0.896</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOT3[A]</td>
<td>uresetn_s0/CLK</td>
</tr>
<tr>
<td>1.961</td>
<td>0.382</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>IOT3[A]</td>
<td style=" font-weight:bold;">uresetn_s0/Q</td>
</tr>
<tr>
<td>5.120</td>
<td>3.159</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C46[3][A]</td>
<td>n106_s1/I2</td>
</tr>
<tr>
<td>5.410</td>
<td>0.290</td>
<td>tINS</td>
<td>RF</td>
<td>22</td>
<td>R21C46[3][A]</td>
<td style=" background: #97FFFF;">n106_s1/F</td>
</tr>
<tr>
<td>5.610</td>
<td>0.200</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C45[3][A]</td>
<td>hubif/frame_clk_s3/I0</td>
</tr>
<tr>
<td>6.025</td>
<td>0.415</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R21C45[3][A]</td>
<td style=" background: #97FFFF;">hubif/frame_clk_s3/F</td>
</tr>
<tr>
<td>6.162</td>
<td>0.137</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C45[2][A]</td>
<td style=" font-weight:bold;">hubif/frame_clk_s1/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clkn[0]</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>22</td>
<td>R21C44[0][A]</td>
<td>clkn_0_s0/Q</td>
</tr>
<tr>
<td>7.077</td>
<td>2.077</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C45[2][A]</td>
<td>hubif/frame_clk_s1/CLK</td>
</tr>
<tr>
<td>7.043</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>hubif/frame_clk_s1</td>
</tr>
<tr>
<td>6.786</td>
<td>-0.256</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R21C45[2][A]</td>
<td>hubif/frame_clk_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.499</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>3</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 43.230%; route: 0.896, 56.770%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.705, 15.380%; route: 3.496, 76.275%; tC2Q: 0.382, 8.345%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.077, 100.000%</td>
</tr>
</table>
<h3>Path10</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.963</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>6.071</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>7.034</td>
</tr>
<tr>
<td class="label">From</td>
<td>uresetn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>hubif/hub_addr_0_s3</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>CLK_IN:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clkn[0]:[F]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>CLK_IN</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>CLK_IN_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>8</td>
<td>IOB12[A]</td>
<td>CLK_IN_ibuf/O</td>
</tr>
<tr>
<td>1.579</td>
<td>0.896</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOT3[A]</td>
<td>uresetn_s0/CLK</td>
</tr>
<tr>
<td>1.961</td>
<td>0.382</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>IOT3[A]</td>
<td style=" font-weight:bold;">uresetn_s0/Q</td>
</tr>
<tr>
<td>5.120</td>
<td>3.159</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C46[3][A]</td>
<td>n106_s1/I2</td>
</tr>
<tr>
<td>5.410</td>
<td>0.290</td>
<td>tINS</td>
<td>RF</td>
<td>22</td>
<td>R21C46[3][A]</td>
<td style=" background: #97FFFF;">n106_s1/F</td>
</tr>
<tr>
<td>5.610</td>
<td>0.200</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C45[0][B]</td>
<td>hubif/n66_s4/I1</td>
</tr>
<tr>
<td>6.071</td>
<td>0.461</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R21C45[0][B]</td>
<td style=" background: #97FFFF;">hubif/n66_s4/F</td>
</tr>
<tr>
<td>6.071</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C45[0][B]</td>
<td style=" font-weight:bold;">hubif/hub_addr_0_s3/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clkn[0]</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>22</td>
<td>R21C44[0][A]</td>
<td>clkn_0_s0/Q</td>
</tr>
<tr>
<td>7.077</td>
<td>2.077</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C45[0][B]</td>
<td>hubif/hub_addr_0_s3/CLK</td>
</tr>
<tr>
<td>7.043</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>hubif/hub_addr_0_s3</td>
</tr>
<tr>
<td>7.034</td>
<td>-0.009</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R21C45[0][B]</td>
<td>hubif/hub_addr_0_s3</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.499</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>3</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 43.230%; route: 0.896, 56.770%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.751, 16.722%; route: 3.359, 74.763%; tC2Q: 0.382, 8.514%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.077, 100.000%</td>
</tr>
</table>
<h3>Path11</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.963</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>6.071</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>7.034</td>
</tr>
<tr>
<td class="label">From</td>
<td>uresetn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>hubif/hub_addr_1_s3</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>CLK_IN:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clkn[0]:[F]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>CLK_IN</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>CLK_IN_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>8</td>
<td>IOB12[A]</td>
<td>CLK_IN_ibuf/O</td>
</tr>
<tr>
<td>1.579</td>
<td>0.896</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOT3[A]</td>
<td>uresetn_s0/CLK</td>
</tr>
<tr>
<td>1.961</td>
<td>0.382</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>IOT3[A]</td>
<td style=" font-weight:bold;">uresetn_s0/Q</td>
</tr>
<tr>
<td>5.120</td>
<td>3.159</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C46[3][A]</td>
<td>n106_s1/I2</td>
</tr>
<tr>
<td>5.410</td>
<td>0.290</td>
<td>tINS</td>
<td>RF</td>
<td>22</td>
<td>R21C46[3][A]</td>
<td style=" background: #97FFFF;">n106_s1/F</td>
</tr>
<tr>
<td>5.610</td>
<td>0.200</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C45[1][A]</td>
<td>hubif/n65_s3/I1</td>
</tr>
<tr>
<td>6.071</td>
<td>0.461</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R21C45[1][A]</td>
<td style=" background: #97FFFF;">hubif/n65_s3/F</td>
</tr>
<tr>
<td>6.071</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C45[1][A]</td>
<td style=" font-weight:bold;">hubif/hub_addr_1_s3/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clkn[0]</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>22</td>
<td>R21C44[0][A]</td>
<td>clkn_0_s0/Q</td>
</tr>
<tr>
<td>7.077</td>
<td>2.077</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C45[1][A]</td>
<td>hubif/hub_addr_1_s3/CLK</td>
</tr>
<tr>
<td>7.043</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>hubif/hub_addr_1_s3</td>
</tr>
<tr>
<td>7.034</td>
<td>-0.009</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R21C45[1][A]</td>
<td>hubif/hub_addr_1_s3</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.499</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>3</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 43.230%; route: 0.896, 56.770%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.751, 16.722%; route: 3.359, 74.763%; tC2Q: 0.382, 8.514%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.077, 100.000%</td>
</tr>
</table>
<h3>Path12</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.963</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>6.071</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>7.034</td>
</tr>
<tr>
<td class="label">From</td>
<td>uresetn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>hubif/hub_addr_6_s3</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>CLK_IN:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clkn[0]:[F]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>CLK_IN</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>CLK_IN_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>8</td>
<td>IOB12[A]</td>
<td>CLK_IN_ibuf/O</td>
</tr>
<tr>
<td>1.579</td>
<td>0.896</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOT3[A]</td>
<td>uresetn_s0/CLK</td>
</tr>
<tr>
<td>1.961</td>
<td>0.382</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>IOT3[A]</td>
<td style=" font-weight:bold;">uresetn_s0/Q</td>
</tr>
<tr>
<td>5.120</td>
<td>3.159</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C46[3][A]</td>
<td>n106_s1/I2</td>
</tr>
<tr>
<td>5.410</td>
<td>0.290</td>
<td>tINS</td>
<td>RF</td>
<td>22</td>
<td>R21C46[3][A]</td>
<td style=" background: #97FFFF;">n106_s1/F</td>
</tr>
<tr>
<td>5.610</td>
<td>0.200</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C45[1][B]</td>
<td>hubif/n60_s3/I1</td>
</tr>
<tr>
<td>6.071</td>
<td>0.461</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R21C45[1][B]</td>
<td style=" background: #97FFFF;">hubif/n60_s3/F</td>
</tr>
<tr>
<td>6.071</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C45[1][B]</td>
<td style=" font-weight:bold;">hubif/hub_addr_6_s3/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clkn[0]</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>22</td>
<td>R21C44[0][A]</td>
<td>clkn_0_s0/Q</td>
</tr>
<tr>
<td>7.077</td>
<td>2.077</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C45[1][B]</td>
<td>hubif/hub_addr_6_s3/CLK</td>
</tr>
<tr>
<td>7.043</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>hubif/hub_addr_6_s3</td>
</tr>
<tr>
<td>7.034</td>
<td>-0.009</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R21C45[1][B]</td>
<td>hubif/hub_addr_6_s3</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.499</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>3</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 43.230%; route: 0.896, 56.770%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.751, 16.722%; route: 3.359, 74.763%; tC2Q: 0.382, 8.514%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.077, 100.000%</td>
</tr>
</table>
<h3>Path13</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.963</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>6.071</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>7.034</td>
</tr>
<tr>
<td class="label">From</td>
<td>uresetn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>hubif/hub_addr_8_s3</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>CLK_IN:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clkn[0]:[F]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>CLK_IN</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>CLK_IN_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>8</td>
<td>IOB12[A]</td>
<td>CLK_IN_ibuf/O</td>
</tr>
<tr>
<td>1.579</td>
<td>0.896</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOT3[A]</td>
<td>uresetn_s0/CLK</td>
</tr>
<tr>
<td>1.961</td>
<td>0.382</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>IOT3[A]</td>
<td style=" font-weight:bold;">uresetn_s0/Q</td>
</tr>
<tr>
<td>5.120</td>
<td>3.159</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C46[3][A]</td>
<td>n106_s1/I2</td>
</tr>
<tr>
<td>5.410</td>
<td>0.290</td>
<td>tINS</td>
<td>RF</td>
<td>22</td>
<td>R21C46[3][A]</td>
<td style=" background: #97FFFF;">n106_s1/F</td>
</tr>
<tr>
<td>5.610</td>
<td>0.200</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C45[0][A]</td>
<td>hubif/n58_s4/I3</td>
</tr>
<tr>
<td>6.071</td>
<td>0.461</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R21C45[0][A]</td>
<td style=" background: #97FFFF;">hubif/n58_s4/F</td>
</tr>
<tr>
<td>6.071</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C45[0][A]</td>
<td style=" font-weight:bold;">hubif/hub_addr_8_s3/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clkn[0]</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>22</td>
<td>R21C44[0][A]</td>
<td>clkn_0_s0/Q</td>
</tr>
<tr>
<td>7.077</td>
<td>2.077</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C45[0][A]</td>
<td>hubif/hub_addr_8_s3/CLK</td>
</tr>
<tr>
<td>7.043</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>hubif/hub_addr_8_s3</td>
</tr>
<tr>
<td>7.034</td>
<td>-0.009</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R21C45[0][A]</td>
<td>hubif/hub_addr_8_s3</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.499</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>3</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 43.230%; route: 0.896, 56.770%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.751, 16.722%; route: 3.359, 74.763%; tC2Q: 0.382, 8.514%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.077, 100.000%</td>
</tr>
</table>
<h3>Path14</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.769</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>11.386</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>12.155</td>
</tr>
<tr>
<td class="label">From</td>
<td>hubif/hub_addr_1_s3</td>
</tr>
<tr>
<td class="label">To</td>
<td>logo_rom/prom_inst_2</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clkn[0]:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clkn[0]:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clkn[0]</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>22</td>
<td>R21C44[0][A]</td>
<td>clkn_0_s0/Q</td>
</tr>
<tr>
<td>7.077</td>
<td>2.077</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C45[1][A]</td>
<td>hubif/hub_addr_1_s3/CLK</td>
</tr>
<tr>
<td>7.511</td>
<td>0.434</td>
<td>tC2Q</td>
<td>FR</td>
<td>8</td>
<td>R21C45[1][A]</td>
<td style=" font-weight:bold;">hubif/hub_addr_1_s3/Q</td>
</tr>
<tr>
<td>11.386</td>
<td>3.875</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[15]</td>
<td style=" font-weight:bold;">logo_rom/prom_inst_2/AD[4]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clkn[0]</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>22</td>
<td>R21C44[0][A]</td>
<td>clkn_0_s0/Q</td>
</tr>
<tr>
<td>12.190</td>
<td>2.190</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[15]</td>
<td>logo_rom/prom_inst_2/CLK</td>
</tr>
<tr>
<td>12.155</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>BSRAM_R28[15]</td>
<td>logo_rom/prom_inst_2</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.112</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.077, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 3.875, 89.933%; tC2Q: 0.434, 10.067%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.190, 100.000%</td>
</tr>
</table>
<h3>Path15</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.870</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>11.285</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>12.155</td>
</tr>
<tr>
<td class="label">From</td>
<td>hubif/hub_addr_8_s3</td>
</tr>
<tr>
<td class="label">To</td>
<td>logo_rom/prom_inst_2</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clkn[0]:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clkn[0]:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clkn[0]</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>22</td>
<td>R21C44[0][A]</td>
<td>clkn_0_s0/Q</td>
</tr>
<tr>
<td>7.077</td>
<td>2.077</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C45[0][A]</td>
<td>hubif/hub_addr_8_s3/CLK</td>
</tr>
<tr>
<td>7.511</td>
<td>0.434</td>
<td>tC2Q</td>
<td>FR</td>
<td>10</td>
<td>R21C45[0][A]</td>
<td style=" font-weight:bold;">hubif/hub_addr_8_s3/Q</td>
</tr>
<tr>
<td>11.285</td>
<td>3.774</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[15]</td>
<td style=" font-weight:bold;">logo_rom/prom_inst_2/AD[11]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clkn[0]</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>22</td>
<td>R21C44[0][A]</td>
<td>clkn_0_s0/Q</td>
</tr>
<tr>
<td>12.190</td>
<td>2.190</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[15]</td>
<td>logo_rom/prom_inst_2/CLK</td>
</tr>
<tr>
<td>12.155</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>BSRAM_R28[15]</td>
<td>logo_rom/prom_inst_2</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.112</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.077, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 3.774, 89.691%; tC2Q: 0.434, 10.309%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.190, 100.000%</td>
</tr>
</table>
<h3>Path16</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.239</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>10.916</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>12.155</td>
</tr>
<tr>
<td class="label">From</td>
<td>hubif/hub_addr_3_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>logo_rom/prom_inst_2</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clkn[0]:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clkn[0]:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clkn[0]</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>22</td>
<td>R21C44[0][A]</td>
<td>clkn_0_s0/Q</td>
</tr>
<tr>
<td>7.041</td>
<td>2.041</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C45[2][B]</td>
<td>hubif/hub_addr_3_s1/CLK</td>
</tr>
<tr>
<td>7.475</td>
<td>0.434</td>
<td>tC2Q</td>
<td>FR</td>
<td>6</td>
<td>R17C45[2][B]</td>
<td style=" font-weight:bold;">hubif/hub_addr_3_s1/Q</td>
</tr>
<tr>
<td>10.916</td>
<td>3.441</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[15]</td>
<td style=" font-weight:bold;">logo_rom/prom_inst_2/AD[6]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clkn[0]</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>22</td>
<td>R21C44[0][A]</td>
<td>clkn_0_s0/Q</td>
</tr>
<tr>
<td>12.190</td>
<td>2.190</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[15]</td>
<td>logo_rom/prom_inst_2/CLK</td>
</tr>
<tr>
<td>12.155</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>BSRAM_R28[15]</td>
<td>logo_rom/prom_inst_2</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.148</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.041, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 3.441, 88.806%; tC2Q: 0.434, 11.194%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.190, 100.000%</td>
</tr>
</table>
<h3>Path17</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.264</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>10.891</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>12.155</td>
</tr>
<tr>
<td class="label">From</td>
<td>hubif/hub_addr_1_s3</td>
</tr>
<tr>
<td class="label">To</td>
<td>logo_rom/prom_inst_1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clkn[0]:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clkn[0]:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clkn[0]</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>22</td>
<td>R21C44[0][A]</td>
<td>clkn_0_s0/Q</td>
</tr>
<tr>
<td>7.077</td>
<td>2.077</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C45[1][A]</td>
<td>hubif/hub_addr_1_s3/CLK</td>
</tr>
<tr>
<td>7.511</td>
<td>0.434</td>
<td>tC2Q</td>
<td>FR</td>
<td>8</td>
<td>R21C45[1][A]</td>
<td style=" font-weight:bold;">hubif/hub_addr_1_s3/Q</td>
</tr>
<tr>
<td>10.891</td>
<td>3.380</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R10[15]</td>
<td style=" font-weight:bold;">logo_rom/prom_inst_1/AD[4]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clkn[0]</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>22</td>
<td>R21C44[0][A]</td>
<td>clkn_0_s0/Q</td>
</tr>
<tr>
<td>12.190</td>
<td>2.190</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R10[15]</td>
<td>logo_rom/prom_inst_1/CLK</td>
</tr>
<tr>
<td>12.155</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>BSRAM_R10[15]</td>
<td>logo_rom/prom_inst_1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.112</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.077, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 3.380, 88.627%; tC2Q: 0.434, 11.373%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.190, 100.000%</td>
</tr>
</table>
<h3>Path18</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.294</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>10.861</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>12.155</td>
</tr>
<tr>
<td class="label">From</td>
<td>hubif/hub_addr_9_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>logo_rom/prom_inst_2</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clkn[0]:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clkn[0]:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clkn[0]</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>22</td>
<td>R21C44[0][A]</td>
<td>clkn_0_s0/Q</td>
</tr>
<tr>
<td>7.041</td>
<td>2.041</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C45[0][B]</td>
<td>hubif/hub_addr_9_s1/CLK</td>
</tr>
<tr>
<td>7.475</td>
<td>0.434</td>
<td>tC2Q</td>
<td>FR</td>
<td>8</td>
<td>R17C45[0][B]</td>
<td style=" font-weight:bold;">hubif/hub_addr_9_s1/Q</td>
</tr>
<tr>
<td>10.861</td>
<td>3.386</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[15]</td>
<td style=" font-weight:bold;">logo_rom/prom_inst_2/AD[12]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clkn[0]</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>22</td>
<td>R21C44[0][A]</td>
<td>clkn_0_s0/Q</td>
</tr>
<tr>
<td>12.190</td>
<td>2.190</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[15]</td>
<td>logo_rom/prom_inst_2/CLK</td>
</tr>
<tr>
<td>12.155</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>BSRAM_R28[15]</td>
<td>logo_rom/prom_inst_2</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.148</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.041, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 3.386, 88.645%; tC2Q: 0.434, 11.355%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.190, 100.000%</td>
</tr>
</table>
<h3>Path19</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.333</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>10.822</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>12.155</td>
</tr>
<tr>
<td class="label">From</td>
<td>hubif/hub_addr_10_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>logo_rom/prom_inst_2</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clkn[0]:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clkn[0]:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clkn[0]</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>22</td>
<td>R21C44[0][A]</td>
<td>clkn_0_s0/Q</td>
</tr>
<tr>
<td>7.043</td>
<td>2.043</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C45[0][B]</td>
<td>hubif/hub_addr_10_s1/CLK</td>
</tr>
<tr>
<td>7.477</td>
<td>0.434</td>
<td>tC2Q</td>
<td>FR</td>
<td>6</td>
<td>R18C45[0][B]</td>
<td style=" font-weight:bold;">hubif/hub_addr_10_s1/Q</td>
</tr>
<tr>
<td>10.822</td>
<td>3.345</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[15]</td>
<td style=" font-weight:bold;">logo_rom/prom_inst_2/AD[13]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clkn[0]</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>22</td>
<td>R21C44[0][A]</td>
<td>clkn_0_s0/Q</td>
</tr>
<tr>
<td>12.190</td>
<td>2.190</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[15]</td>
<td>logo_rom/prom_inst_2/CLK</td>
</tr>
<tr>
<td>12.155</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>BSRAM_R28[15]</td>
<td>logo_rom/prom_inst_2</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.147</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.043, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 3.345, 88.521%; tC2Q: 0.434, 11.479%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.190, 100.000%</td>
</tr>
</table>
<h3>Path20</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.484</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>10.671</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>12.155</td>
</tr>
<tr>
<td class="label">From</td>
<td>hubif/hub_addr_7_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>logo_rom/prom_inst_2</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clkn[0]:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clkn[0]:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clkn[0]</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>22</td>
<td>R21C44[0][A]</td>
<td>clkn_0_s0/Q</td>
</tr>
<tr>
<td>7.041</td>
<td>2.041</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C45[1][A]</td>
<td>hubif/hub_addr_7_s1/CLK</td>
</tr>
<tr>
<td>7.475</td>
<td>0.434</td>
<td>tC2Q</td>
<td>FR</td>
<td>10</td>
<td>R17C45[1][A]</td>
<td style=" font-weight:bold;">hubif/hub_addr_7_s1/Q</td>
</tr>
<tr>
<td>10.671</td>
<td>3.196</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[15]</td>
<td style=" font-weight:bold;">logo_rom/prom_inst_2/AD[10]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clkn[0]</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>22</td>
<td>R21C44[0][A]</td>
<td>clkn_0_s0/Q</td>
</tr>
<tr>
<td>12.190</td>
<td>2.190</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[15]</td>
<td>logo_rom/prom_inst_2/CLK</td>
</tr>
<tr>
<td>12.155</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>BSRAM_R28[15]</td>
<td>logo_rom/prom_inst_2</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.148</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.041, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 3.196, 88.051%; tC2Q: 0.434, 11.949%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.190, 100.000%</td>
</tr>
</table>
<h3>Path21</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.819</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>10.326</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>12.146</td>
</tr>
<tr>
<td class="label">From</td>
<td>hubif/hub_addr_6_s3</td>
</tr>
<tr>
<td class="label">To</td>
<td>logo_rom/prom_inst_3</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clkn[0]:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clkn[0]:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clkn[0]</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>22</td>
<td>R21C44[0][A]</td>
<td>clkn_0_s0/Q</td>
</tr>
<tr>
<td>7.077</td>
<td>2.077</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C45[1][B]</td>
<td>hubif/hub_addr_6_s3/CLK</td>
</tr>
<tr>
<td>7.511</td>
<td>0.434</td>
<td>tC2Q</td>
<td>FR</td>
<td>12</td>
<td>R21C45[1][B]</td>
<td style=" font-weight:bold;">hubif/hub_addr_6_s3/Q</td>
</tr>
<tr>
<td>10.326</td>
<td>2.815</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R10[16]</td>
<td style=" font-weight:bold;">logo_rom/prom_inst_3/AD[9]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clkn[0]</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>22</td>
<td>R21C44[0][A]</td>
<td>clkn_0_s0/Q</td>
</tr>
<tr>
<td>12.180</td>
<td>2.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R10[16]</td>
<td>logo_rom/prom_inst_3/CLK</td>
</tr>
<tr>
<td>12.146</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>BSRAM_R10[16]</td>
<td>logo_rom/prom_inst_3</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.103</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.077, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.815, 86.649%; tC2Q: 0.434, 13.351%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.180, 100.000%</td>
</tr>
</table>
<h3>Path22</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.867</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>10.279</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>12.146</td>
</tr>
<tr>
<td class="label">From</td>
<td>hubif/hub_addr_8_s3</td>
</tr>
<tr>
<td class="label">To</td>
<td>logo_rom/prom_inst_3</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clkn[0]:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clkn[0]:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clkn[0]</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>22</td>
<td>R21C44[0][A]</td>
<td>clkn_0_s0/Q</td>
</tr>
<tr>
<td>7.077</td>
<td>2.077</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C45[0][A]</td>
<td>hubif/hub_addr_8_s3/CLK</td>
</tr>
<tr>
<td>7.511</td>
<td>0.434</td>
<td>tC2Q</td>
<td>FR</td>
<td>10</td>
<td>R21C45[0][A]</td>
<td style=" font-weight:bold;">hubif/hub_addr_8_s3/Q</td>
</tr>
<tr>
<td>10.279</td>
<td>2.768</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R10[16]</td>
<td style=" font-weight:bold;">logo_rom/prom_inst_3/AD[11]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clkn[0]</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>22</td>
<td>R21C44[0][A]</td>
<td>clkn_0_s0/Q</td>
</tr>
<tr>
<td>12.180</td>
<td>2.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R10[16]</td>
<td>logo_rom/prom_inst_3/CLK</td>
</tr>
<tr>
<td>12.146</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>BSRAM_R10[16]</td>
<td>logo_rom/prom_inst_3</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.103</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.077, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.768, 86.451%; tC2Q: 0.434, 13.549%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.180, 100.000%</td>
</tr>
</table>
<h3>Path23</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.066</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>10.089</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>12.155</td>
</tr>
<tr>
<td class="label">From</td>
<td>hubif/hub_addr_8_s3</td>
</tr>
<tr>
<td class="label">To</td>
<td>logo_rom/prom_inst_1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clkn[0]:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clkn[0]:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clkn[0]</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>22</td>
<td>R21C44[0][A]</td>
<td>clkn_0_s0/Q</td>
</tr>
<tr>
<td>7.077</td>
<td>2.077</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C45[0][A]</td>
<td>hubif/hub_addr_8_s3/CLK</td>
</tr>
<tr>
<td>7.511</td>
<td>0.434</td>
<td>tC2Q</td>
<td>FR</td>
<td>10</td>
<td>R21C45[0][A]</td>
<td style=" font-weight:bold;">hubif/hub_addr_8_s3/Q</td>
</tr>
<tr>
<td>10.089</td>
<td>2.578</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R10[15]</td>
<td style=" font-weight:bold;">logo_rom/prom_inst_1/AD[11]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clkn[0]</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>22</td>
<td>R21C44[0][A]</td>
<td>clkn_0_s0/Q</td>
</tr>
<tr>
<td>12.190</td>
<td>2.190</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R10[15]</td>
<td>logo_rom/prom_inst_1/CLK</td>
</tr>
<tr>
<td>12.155</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>BSRAM_R10[15]</td>
<td>logo_rom/prom_inst_1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.112</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.077, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.578, 85.596%; tC2Q: 0.434, 14.404%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.190, 100.000%</td>
</tr>
</table>
<h3>Path24</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.117</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>10.029</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>12.146</td>
</tr>
<tr>
<td class="label">From</td>
<td>hubif/hub_addr_2_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>logo_rom/prom_inst_3</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clkn[0]:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clkn[0]:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clkn[0]</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>22</td>
<td>R21C44[0][A]</td>
<td>clkn_0_s0/Q</td>
</tr>
<tr>
<td>7.080</td>
<td>2.080</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R20C45[2][A]</td>
<td>hubif/hub_addr_2_s1/CLK</td>
</tr>
<tr>
<td>7.514</td>
<td>0.434</td>
<td>tC2Q</td>
<td>FR</td>
<td>7</td>
<td>R20C45[2][A]</td>
<td style=" font-weight:bold;">hubif/hub_addr_2_s1/Q</td>
</tr>
<tr>
<td>10.029</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R10[16]</td>
<td style=" font-weight:bold;">logo_rom/prom_inst_3/AD[5]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clkn[0]</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>22</td>
<td>R21C44[0][A]</td>
<td>clkn_0_s0/Q</td>
</tr>
<tr>
<td>12.180</td>
<td>2.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R10[16]</td>
<td>logo_rom/prom_inst_3/CLK</td>
</tr>
<tr>
<td>12.146</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>BSRAM_R10[16]</td>
<td>logo_rom/prom_inst_3</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.100</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.080, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.515, 85.290%; tC2Q: 0.434, 14.710%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.180, 100.000%</td>
</tr>
</table>
<h3>Path25</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.209</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>9.946</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>12.155</td>
</tr>
<tr>
<td class="label">From</td>
<td>hubif/hub_addr_6_s3</td>
</tr>
<tr>
<td class="label">To</td>
<td>logo_rom/prom_inst_1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clkn[0]:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clkn[0]:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clkn[0]</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>22</td>
<td>R21C44[0][A]</td>
<td>clkn_0_s0/Q</td>
</tr>
<tr>
<td>7.077</td>
<td>2.077</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C45[1][B]</td>
<td>hubif/hub_addr_6_s3/CLK</td>
</tr>
<tr>
<td>7.511</td>
<td>0.434</td>
<td>tC2Q</td>
<td>FR</td>
<td>12</td>
<td>R21C45[1][B]</td>
<td style=" font-weight:bold;">hubif/hub_addr_6_s3/Q</td>
</tr>
<tr>
<td>9.946</td>
<td>2.435</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R10[15]</td>
<td style=" font-weight:bold;">logo_rom/prom_inst_1/AD[9]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clkn[0]</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>22</td>
<td>R21C44[0][A]</td>
<td>clkn_0_s0/Q</td>
</tr>
<tr>
<td>12.190</td>
<td>2.190</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R10[15]</td>
<td>logo_rom/prom_inst_1/CLK</td>
</tr>
<tr>
<td>12.155</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>BSRAM_R10[15]</td>
<td>logo_rom/prom_inst_1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.112</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.077, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.435, 84.880%; tC2Q: 0.434, 15.120%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.190, 100.000%</td>
</tr>
</table>
<h3><a name="Hold_Analysis">Hold Analysis Report</a></h3>
<h4>Report Command:report_timing -hold -max_paths 25 -max_common_paths 1</h4>
<h3>Path1</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-0.909</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.199</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.108</td>
</tr>
<tr>
<td class="label">From</td>
<td>hubif/n51_s2</td>
</tr>
<tr>
<td class="label">To</td>
<td>clkn_0_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clkn[0]:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>CLK_IN:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clkn[0]</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>22</td>
<td>R21C44[0][A]</td>
<td>clkn_0_s0/Q</td>
</tr>
<tr>
<td>0.008</td>
<td>0.008</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C44[0][A]</td>
<td style=" font-weight:bold;">hubif/n51_s2/I0</td>
</tr>
<tr>
<td>0.199</td>
<td>0.191</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R21C44[0][A]</td>
<td style=" background: #97FFFF;">hubif/n51_s2/F</td>
</tr>
<tr>
<td>0.199</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C44[0][A]</td>
<td style=" font-weight:bold;">clkn_0_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>CLK_IN</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>CLK_IN_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>8</td>
<td>IOB12[A]</td>
<td>CLK_IN_ibuf/O</td>
</tr>
<tr>
<td>1.072</td>
<td>0.396</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C44[0][A]</td>
<td>clkn_0_s0/CLK</td>
</tr>
<tr>
<td>1.107</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>clkn_0_s0</td>
</tr>
<tr>
<td>1.108</td>
<td>0.001</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R21C44[0][A]</td>
<td>clkn_0_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.072</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.191, 96.226%; route: 0.000, 0.000%; tC2Q: 0.008, 3.774%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 63.028%; route: 0.396, 36.972%</td>
</tr>
</table>
<h3>Path2</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.339</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>6.644</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>6.305</td>
</tr>
<tr>
<td class="label">From</td>
<td>hubif/hub_addr_1_s3</td>
</tr>
<tr>
<td class="label">To</td>
<td>hubif/hub_addr_1_s3</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clkn[0]:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clkn[0]:[F]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clkn[0]</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>22</td>
<td>R21C44[0][A]</td>
<td>clkn_0_s0/Q</td>
</tr>
<tr>
<td>6.250</td>
<td>1.250</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C45[1][A]</td>
<td>hubif/hub_addr_1_s3/CLK</td>
</tr>
<tr>
<td>6.445</td>
<td>0.195</td>
<td>tC2Q</td>
<td>FF</td>
<td>8</td>
<td>R21C45[1][A]</td>
<td style=" font-weight:bold;">hubif/hub_addr_1_s3/Q</td>
</tr>
<tr>
<td>6.453</td>
<td>0.008</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C45[1][A]</td>
<td>hubif/n65_s3/I2</td>
</tr>
<tr>
<td>6.644</td>
<td>0.191</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R21C45[1][A]</td>
<td style=" background: #97FFFF;">hubif/n65_s3/F</td>
</tr>
<tr>
<td>6.644</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C45[1][A]</td>
<td style=" font-weight:bold;">hubif/hub_addr_1_s3/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clkn[0]</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>22</td>
<td>R21C44[0][A]</td>
<td>clkn_0_s0/Q</td>
</tr>
<tr>
<td>6.250</td>
<td>1.250</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C45[1][A]</td>
<td>hubif/hub_addr_1_s3/CLK</td>
</tr>
<tr>
<td>6.305</td>
<td>0.055</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R21C45[1][A]</td>
<td>hubif/hub_addr_1_s3</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.250, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.191, 48.571%; route: 0.008, 1.905%; tC2Q: 0.195, 49.524%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.250, 100.000%</td>
</tr>
</table>
<h3>Path3</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.339</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>6.644</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>6.305</td>
</tr>
<tr>
<td class="label">From</td>
<td>hubif/hub_addr_8_s3</td>
</tr>
<tr>
<td class="label">To</td>
<td>hubif/hub_addr_8_s3</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clkn[0]:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clkn[0]:[F]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clkn[0]</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>22</td>
<td>R21C44[0][A]</td>
<td>clkn_0_s0/Q</td>
</tr>
<tr>
<td>6.250</td>
<td>1.250</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C45[0][A]</td>
<td>hubif/hub_addr_8_s3/CLK</td>
</tr>
<tr>
<td>6.445</td>
<td>0.195</td>
<td>tC2Q</td>
<td>FF</td>
<td>10</td>
<td>R21C45[0][A]</td>
<td style=" font-weight:bold;">hubif/hub_addr_8_s3/Q</td>
</tr>
<tr>
<td>6.453</td>
<td>0.008</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C45[0][A]</td>
<td>hubif/n58_s4/I0</td>
</tr>
<tr>
<td>6.644</td>
<td>0.191</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R21C45[0][A]</td>
<td style=" background: #97FFFF;">hubif/n58_s4/F</td>
</tr>
<tr>
<td>6.644</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C45[0][A]</td>
<td style=" font-weight:bold;">hubif/hub_addr_8_s3/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clkn[0]</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>22</td>
<td>R21C44[0][A]</td>
<td>clkn_0_s0/Q</td>
</tr>
<tr>
<td>6.250</td>
<td>1.250</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C45[0][A]</td>
<td>hubif/hub_addr_8_s3/CLK</td>
</tr>
<tr>
<td>6.305</td>
<td>0.055</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R21C45[0][A]</td>
<td>hubif/hub_addr_8_s3</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.250, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.191, 48.571%; route: 0.008, 1.905%; tC2Q: 0.195, 49.524%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.250, 100.000%</td>
</tr>
</table>
<h3>Path4</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.343</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>6.624</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>6.281</td>
</tr>
<tr>
<td class="label">From</td>
<td>hubif/state_1_s5</td>
</tr>
<tr>
<td class="label">To</td>
<td>hubif/state_1_s5</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clkn[0]:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clkn[0]:[F]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clkn[0]</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>22</td>
<td>R21C44[0][A]</td>
<td>clkn_0_s0/Q</td>
</tr>
<tr>
<td>6.226</td>
<td>1.226</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C44[0][A]</td>
<td>hubif/state_1_s5/CLK</td>
</tr>
<tr>
<td>6.421</td>
<td>0.195</td>
<td>tC2Q</td>
<td>FF</td>
<td>6</td>
<td>R17C44[0][A]</td>
<td style=" font-weight:bold;">hubif/state_1_s5/Q</td>
</tr>
<tr>
<td>6.433</td>
<td>0.011</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C44[0][A]</td>
<td>hubif/n219_s3/I0</td>
</tr>
<tr>
<td>6.624</td>
<td>0.191</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R17C44[0][A]</td>
<td style=" background: #97FFFF;">hubif/n219_s3/F</td>
</tr>
<tr>
<td>6.624</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C44[0][A]</td>
<td style=" font-weight:bold;">hubif/state_1_s5/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clkn[0]</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>22</td>
<td>R21C44[0][A]</td>
<td>clkn_0_s0/Q</td>
</tr>
<tr>
<td>6.226</td>
<td>1.226</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C44[0][A]</td>
<td>hubif/state_1_s5/CLK</td>
</tr>
<tr>
<td>6.281</td>
<td>0.055</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R17C44[0][A]</td>
<td>hubif/state_1_s5</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.226, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.191, 48.113%; route: 0.011, 2.830%; tC2Q: 0.195, 49.057%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.226, 100.000%</td>
</tr>
</table>
<h3>Path5</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.343</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>6.619</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>6.276</td>
</tr>
<tr>
<td class="label">From</td>
<td>hubif/hub_addr_7_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>hubif/hub_addr_7_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clkn[0]:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clkn[0]:[F]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clkn[0]</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>22</td>
<td>R21C44[0][A]</td>
<td>clkn_0_s0/Q</td>
</tr>
<tr>
<td>6.221</td>
<td>1.221</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C45[1][A]</td>
<td>hubif/hub_addr_7_s1/CLK</td>
</tr>
<tr>
<td>6.416</td>
<td>0.195</td>
<td>tC2Q</td>
<td>FF</td>
<td>10</td>
<td>R17C45[1][A]</td>
<td style=" font-weight:bold;">hubif/hub_addr_7_s1/Q</td>
</tr>
<tr>
<td>6.428</td>
<td>0.011</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C45[1][A]</td>
<td>hubif/n59_s1/I2</td>
</tr>
<tr>
<td>6.619</td>
<td>0.191</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R17C45[1][A]</td>
<td style=" background: #97FFFF;">hubif/n59_s1/F</td>
</tr>
<tr>
<td>6.619</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C45[1][A]</td>
<td style=" font-weight:bold;">hubif/hub_addr_7_s1/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clkn[0]</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>22</td>
<td>R21C44[0][A]</td>
<td>clkn_0_s0/Q</td>
</tr>
<tr>
<td>6.221</td>
<td>1.221</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C45[1][A]</td>
<td>hubif/hub_addr_7_s1/CLK</td>
</tr>
<tr>
<td>6.276</td>
<td>0.055</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R17C45[1][A]</td>
<td>hubif/hub_addr_7_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.221, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.191, 48.113%; route: 0.011, 2.830%; tC2Q: 0.195, 49.057%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.221, 100.000%</td>
</tr>
</table>
<h3>Path6</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.346</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>6.654</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>6.307</td>
</tr>
<tr>
<td class="label">From</td>
<td>hubif/state_0_s3</td>
</tr>
<tr>
<td class="label">To</td>
<td>hubif/state_0_s3</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clkn[0]:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clkn[0]:[F]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clkn[0]</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>22</td>
<td>R21C44[0][A]</td>
<td>clkn_0_s0/Q</td>
</tr>
<tr>
<td>6.253</td>
<td>1.253</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R20C45[0][A]</td>
<td>hubif/state_0_s3/CLK</td>
</tr>
<tr>
<td>6.448</td>
<td>0.195</td>
<td>tC2Q</td>
<td>FF</td>
<td>11</td>
<td>R20C45[0][A]</td>
<td style=" font-weight:bold;">hubif/state_0_s3/Q</td>
</tr>
<tr>
<td>6.463</td>
<td>0.015</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R20C45[0][A]</td>
<td>hubif/n146_s1/I2</td>
</tr>
<tr>
<td>6.654</td>
<td>0.191</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R20C45[0][A]</td>
<td style=" background: #97FFFF;">hubif/n146_s1/F</td>
</tr>
<tr>
<td>6.654</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R20C45[0][A]</td>
<td style=" font-weight:bold;">hubif/state_0_s3/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clkn[0]</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>22</td>
<td>R21C44[0][A]</td>
<td>clkn_0_s0/Q</td>
</tr>
<tr>
<td>6.253</td>
<td>1.253</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R20C45[0][A]</td>
<td>hubif/state_0_s3/CLK</td>
</tr>
<tr>
<td>6.307</td>
<td>0.055</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R20C45[0][A]</td>
<td>hubif/state_0_s3</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.253, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.191, 47.664%; route: 0.015, 3.738%; tC2Q: 0.195, 48.598%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.253, 100.000%</td>
</tr>
</table>
<h3>Path7</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.374</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.720</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.346</td>
</tr>
<tr>
<td class="label">From</td>
<td>frame_count_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>frame_count_0_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>frame_clk_Z:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>frame_clk_Z:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>frame_clk_Z</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>12</td>
<td>R21C45[2][A]</td>
<td>hubif/frame_clk_s1/Q</td>
</tr>
<tr>
<td>1.345</td>
<td>1.345</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C47[0][A]</td>
<td>frame_count_0_s0/CLK</td>
</tr>
<tr>
<td>1.521</td>
<td>0.176</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R21C47[0][A]</td>
<td style=" font-weight:bold;">frame_count_0_s0/Q</td>
</tr>
<tr>
<td>1.529</td>
<td>0.008</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C47[0][A]</td>
<td>n117_s2/I0</td>
</tr>
<tr>
<td>1.720</td>
<td>0.191</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R21C47[0][A]</td>
<td style=" background: #97FFFF;">n117_s2/F</td>
</tr>
<tr>
<td>1.720</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C47[0][A]</td>
<td style=" font-weight:bold;">frame_count_0_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>frame_clk_Z</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>12</td>
<td>R21C45[2][A]</td>
<td>hubif/frame_clk_s1/Q</td>
</tr>
<tr>
<td>1.345</td>
<td>1.345</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C47[0][A]</td>
<td>frame_count_0_s0/CLK</td>
</tr>
<tr>
<td>1.346</td>
<td>0.001</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R21C47[0][A]</td>
<td>frame_count_0_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.345, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.345, 100.000%</td>
</tr>
</table>
<h3>Path8</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.413</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>6.720</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>6.307</td>
</tr>
<tr>
<td class="label">From</td>
<td>hubif/hub_addr_2_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>hubif/hub_addr_2_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clkn[0]:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clkn[0]:[F]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clkn[0]</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>22</td>
<td>R21C44[0][A]</td>
<td>clkn_0_s0/Q</td>
</tr>
<tr>
<td>6.253</td>
<td>1.253</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R20C45[2][A]</td>
<td>hubif/hub_addr_2_s1/CLK</td>
</tr>
<tr>
<td>6.448</td>
<td>0.195</td>
<td>tC2Q</td>
<td>FF</td>
<td>7</td>
<td>R20C45[2][A]</td>
<td style=" font-weight:bold;">hubif/hub_addr_2_s1/Q</td>
</tr>
<tr>
<td>6.463</td>
<td>0.015</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R20C45[2][A]</td>
<td>hubif/n64_s3/I1</td>
</tr>
<tr>
<td>6.720</td>
<td>0.257</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R20C45[2][A]</td>
<td style=" background: #97FFFF;">hubif/n64_s3/F</td>
</tr>
<tr>
<td>6.720</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R20C45[2][A]</td>
<td style=" font-weight:bold;">hubif/hub_addr_2_s1/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clkn[0]</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>22</td>
<td>R21C44[0][A]</td>
<td>clkn_0_s0/Q</td>
</tr>
<tr>
<td>6.253</td>
<td>1.253</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R20C45[2][A]</td>
<td>hubif/hub_addr_2_s1/CLK</td>
</tr>
<tr>
<td>6.307</td>
<td>0.055</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R20C45[2][A]</td>
<td>hubif/hub_addr_2_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.253, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.257, 55.080%; route: 0.015, 3.209%; tC2Q: 0.195, 41.711%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.253, 100.000%</td>
</tr>
</table>
<h3>Path9</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.413</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>6.689</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>6.276</td>
</tr>
<tr>
<td class="label">From</td>
<td>hubif/hub_addr_4_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>hubif/hub_addr_4_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clkn[0]:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clkn[0]:[F]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clkn[0]</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>22</td>
<td>R21C44[0][A]</td>
<td>clkn_0_s0/Q</td>
</tr>
<tr>
<td>6.221</td>
<td>1.221</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C45[2][A]</td>
<td>hubif/hub_addr_4_s1/CLK</td>
</tr>
<tr>
<td>6.416</td>
<td>0.195</td>
<td>tC2Q</td>
<td>FF</td>
<td>8</td>
<td>R17C45[2][A]</td>
<td style=" font-weight:bold;">hubif/hub_addr_4_s1/Q</td>
</tr>
<tr>
<td>6.431</td>
<td>0.015</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C45[2][A]</td>
<td>hubif/n62_s1/I1</td>
</tr>
<tr>
<td>6.689</td>
<td>0.257</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R17C45[2][A]</td>
<td style=" background: #97FFFF;">hubif/n62_s1/F</td>
</tr>
<tr>
<td>6.689</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C45[2][A]</td>
<td style=" font-weight:bold;">hubif/hub_addr_4_s1/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clkn[0]</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>22</td>
<td>R21C44[0][A]</td>
<td>clkn_0_s0/Q</td>
</tr>
<tr>
<td>6.221</td>
<td>1.221</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C45[2][A]</td>
<td>hubif/hub_addr_4_s1/CLK</td>
</tr>
<tr>
<td>6.276</td>
<td>0.055</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R17C45[2][A]</td>
<td>hubif/hub_addr_4_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.221, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.257, 55.080%; route: 0.015, 3.209%; tC2Q: 0.195, 41.711%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.221, 100.000%</td>
</tr>
</table>
<h3>Path10</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.458</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>6.734</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>6.276</td>
</tr>
<tr>
<td class="label">From</td>
<td>hubif/hub_addr_9_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>hubif/hub_addr_9_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clkn[0]:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clkn[0]:[F]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clkn[0]</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>22</td>
<td>R21C44[0][A]</td>
<td>clkn_0_s0/Q</td>
</tr>
<tr>
<td>6.221</td>
<td>1.221</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C45[0][B]</td>
<td>hubif/hub_addr_9_s1/CLK</td>
</tr>
<tr>
<td>6.416</td>
<td>0.195</td>
<td>tC2Q</td>
<td>FF</td>
<td>8</td>
<td>R17C45[0][B]</td>
<td style=" font-weight:bold;">hubif/hub_addr_9_s1/Q</td>
</tr>
<tr>
<td>6.424</td>
<td>0.008</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C45[0][B]</td>
<td>hubif/n57_s1/I2</td>
</tr>
<tr>
<td>6.734</td>
<td>0.310</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R17C45[0][B]</td>
<td style=" background: #97FFFF;">hubif/n57_s1/F</td>
</tr>
<tr>
<td>6.734</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C45[0][B]</td>
<td style=" font-weight:bold;">hubif/hub_addr_9_s1/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clkn[0]</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>22</td>
<td>R21C44[0][A]</td>
<td>clkn_0_s0/Q</td>
</tr>
<tr>
<td>6.221</td>
<td>1.221</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C45[0][B]</td>
<td>hubif/hub_addr_9_s1/CLK</td>
</tr>
<tr>
<td>6.276</td>
<td>0.055</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R17C45[0][B]</td>
<td>hubif/hub_addr_9_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.221, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.310, 60.488%; route: 0.008, 1.463%; tC2Q: 0.195, 38.049%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.221, 100.000%</td>
</tr>
</table>
<h3>Path11</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.461</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>6.766</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>6.305</td>
</tr>
<tr>
<td class="label">From</td>
<td>hubif/hub_addr_0_s3</td>
</tr>
<tr>
<td class="label">To</td>
<td>hubif/hub_addr_0_s3</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clkn[0]:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clkn[0]:[F]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clkn[0]</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>22</td>
<td>R21C44[0][A]</td>
<td>clkn_0_s0/Q</td>
</tr>
<tr>
<td>6.250</td>
<td>1.250</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C45[0][B]</td>
<td>hubif/hub_addr_0_s3/CLK</td>
</tr>
<tr>
<td>6.445</td>
<td>0.195</td>
<td>tC2Q</td>
<td>FF</td>
<td>9</td>
<td>R21C45[0][B]</td>
<td style=" font-weight:bold;">hubif/hub_addr_0_s3/Q</td>
</tr>
<tr>
<td>6.456</td>
<td>0.011</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C45[0][B]</td>
<td>hubif/n66_s4/I2</td>
</tr>
<tr>
<td>6.766</td>
<td>0.310</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R21C45[0][B]</td>
<td style=" background: #97FFFF;">hubif/n66_s4/F</td>
</tr>
<tr>
<td>6.766</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C45[0][B]</td>
<td style=" font-weight:bold;">hubif/hub_addr_0_s3/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clkn[0]</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>22</td>
<td>R21C44[0][A]</td>
<td>clkn_0_s0/Q</td>
</tr>
<tr>
<td>6.250</td>
<td>1.250</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C45[0][B]</td>
<td>hubif/hub_addr_0_s3/CLK</td>
</tr>
<tr>
<td>6.305</td>
<td>0.055</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R21C45[0][B]</td>
<td>hubif/hub_addr_0_s3</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.250, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.310, 60.048%; route: 0.011, 2.179%; tC2Q: 0.195, 37.772%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.250, 100.000%</td>
</tr>
</table>
<h3>Path12</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.461</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>6.766</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>6.305</td>
</tr>
<tr>
<td class="label">From</td>
<td>hubif/hub_addr_6_s3</td>
</tr>
<tr>
<td class="label">To</td>
<td>hubif/hub_addr_6_s3</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clkn[0]:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clkn[0]:[F]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clkn[0]</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>22</td>
<td>R21C44[0][A]</td>
<td>clkn_0_s0/Q</td>
</tr>
<tr>
<td>6.250</td>
<td>1.250</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C45[1][B]</td>
<td>hubif/hub_addr_6_s3/CLK</td>
</tr>
<tr>
<td>6.445</td>
<td>0.195</td>
<td>tC2Q</td>
<td>FF</td>
<td>12</td>
<td>R21C45[1][B]</td>
<td style=" font-weight:bold;">hubif/hub_addr_6_s3/Q</td>
</tr>
<tr>
<td>6.456</td>
<td>0.011</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C45[1][B]</td>
<td>hubif/n60_s3/I2</td>
</tr>
<tr>
<td>6.766</td>
<td>0.310</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R21C45[1][B]</td>
<td style=" background: #97FFFF;">hubif/n60_s3/F</td>
</tr>
<tr>
<td>6.766</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C45[1][B]</td>
<td style=" font-weight:bold;">hubif/hub_addr_6_s3/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clkn[0]</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>22</td>
<td>R21C44[0][A]</td>
<td>clkn_0_s0/Q</td>
</tr>
<tr>
<td>6.250</td>
<td>1.250</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C45[1][B]</td>
<td>hubif/hub_addr_6_s3/CLK</td>
</tr>
<tr>
<td>6.305</td>
<td>0.055</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R21C45[1][B]</td>
<td>hubif/hub_addr_6_s3</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.250, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.310, 60.048%; route: 0.011, 2.179%; tC2Q: 0.195, 37.772%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.250, 100.000%</td>
</tr>
</table>
<h3>Path13</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.461</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>6.739</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>6.278</td>
</tr>
<tr>
<td class="label">From</td>
<td>hubif/hub_addr_10_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>hubif/hub_addr_10_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clkn[0]:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clkn[0]:[F]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clkn[0]</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>22</td>
<td>R21C44[0][A]</td>
<td>clkn_0_s0/Q</td>
</tr>
<tr>
<td>6.223</td>
<td>1.223</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C45[0][B]</td>
<td>hubif/hub_addr_10_s1/CLK</td>
</tr>
<tr>
<td>6.418</td>
<td>0.195</td>
<td>tC2Q</td>
<td>FF</td>
<td>6</td>
<td>R18C45[0][B]</td>
<td style=" font-weight:bold;">hubif/hub_addr_10_s1/Q</td>
</tr>
<tr>
<td>6.429</td>
<td>0.011</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C45[0][B]</td>
<td>hubif/n56_s1/I2</td>
</tr>
<tr>
<td>6.739</td>
<td>0.310</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R18C45[0][B]</td>
<td style=" background: #97FFFF;">hubif/n56_s1/F</td>
</tr>
<tr>
<td>6.739</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C45[0][B]</td>
<td style=" font-weight:bold;">hubif/hub_addr_10_s1/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clkn[0]</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>22</td>
<td>R21C44[0][A]</td>
<td>clkn_0_s0/Q</td>
</tr>
<tr>
<td>6.223</td>
<td>1.223</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C45[0][B]</td>
<td>hubif/hub_addr_10_s1/CLK</td>
</tr>
<tr>
<td>6.278</td>
<td>0.055</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R18C45[0][B]</td>
<td>hubif/hub_addr_10_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.223, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.310, 60.048%; route: 0.011, 2.179%; tC2Q: 0.195, 37.772%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.223, 100.000%</td>
</tr>
</table>
<h3>Path14</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.529</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.825</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.296</td>
</tr>
<tr>
<td class="label">From</td>
<td>frame_count_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>frame_count_3_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>frame_clk_Z:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>frame_clk_Z:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>frame_clk_Z</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>12</td>
<td>R21C45[2][A]</td>
<td>hubif/frame_clk_s1/Q</td>
</tr>
<tr>
<td>1.320</td>
<td>1.320</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C47[1][A]</td>
<td>frame_count_3_s0/CLK</td>
</tr>
<tr>
<td>1.496</td>
<td>0.176</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>R18C47[1][A]</td>
<td style=" font-weight:bold;">frame_count_3_s0/Q</td>
</tr>
<tr>
<td>1.500</td>
<td>0.004</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R18C47[1][A]</td>
<td>n114_s/I1</td>
</tr>
<tr>
<td>1.825</td>
<td>0.325</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R18C47[1][A]</td>
<td style=" background: #97FFFF;">n114_s/SUM</td>
</tr>
<tr>
<td>1.825</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C47[1][A]</td>
<td style=" font-weight:bold;">frame_count_3_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>frame_clk_Z</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>12</td>
<td>R21C45[2][A]</td>
<td>hubif/frame_clk_s1/Q</td>
</tr>
<tr>
<td>1.320</td>
<td>1.320</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C47[1][A]</td>
<td>frame_count_3_s0/CLK</td>
</tr>
<tr>
<td>1.296</td>
<td>-0.024</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R18C47[1][A]</td>
<td>frame_count_3_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.320, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.325, 64.356%; route: 0.004, 0.743%; tC2Q: 0.176, 34.901%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.320, 100.000%</td>
</tr>
</table>
<h3>Path15</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.532</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.590</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.057</td>
</tr>
<tr>
<td class="label">From</td>
<td>reset_cnt_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>reset_cnt_2_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>CLK_IN:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>CLK_IN:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>CLK_IN</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>CLK_IN_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>8</td>
<td>IOB12[A]</td>
<td>CLK_IN_ibuf/O</td>
</tr>
<tr>
<td>1.081</td>
<td>0.406</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C46[1][A]</td>
<td>reset_cnt_2_s0/CLK</td>
</tr>
<tr>
<td>1.257</td>
<td>0.176</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R21C46[1][A]</td>
<td style=" font-weight:bold;">reset_cnt_2_s0/Q</td>
</tr>
<tr>
<td>1.265</td>
<td>0.008</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R21C46[1][A]</td>
<td>n12_s/I1</td>
</tr>
<tr>
<td>1.590</td>
<td>0.325</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R21C46[1][A]</td>
<td style=" background: #97FFFF;">n12_s/SUM</td>
</tr>
<tr>
<td>1.590</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C46[1][A]</td>
<td style=" font-weight:bold;">reset_cnt_2_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>CLK_IN</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>CLK_IN_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>8</td>
<td>IOB12[A]</td>
<td>CLK_IN_ibuf/O</td>
</tr>
<tr>
<td>1.081</td>
<td>0.406</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C46[1][A]</td>
<td>reset_cnt_2_s0/CLK</td>
</tr>
<tr>
<td>1.057</td>
<td>-0.024</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R21C46[1][A]</td>
<td>reset_cnt_2_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 62.481%; route: 0.406, 37.519%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.325, 63.882%; route: 0.008, 1.474%; tC2Q: 0.176, 34.644%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 62.481%; route: 0.406, 37.519%</td>
</tr>
</table>
<h3>Path16</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.539</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>6.796</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>6.258</td>
</tr>
<tr>
<td class="label">From</td>
<td>hubif/hub_addr_4_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>hubif/hub_addr_5_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clkn[0]:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clkn[0]:[F]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clkn[0]</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>22</td>
<td>R21C44[0][A]</td>
<td>clkn_0_s0/Q</td>
</tr>
<tr>
<td>6.221</td>
<td>1.221</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C45[2][A]</td>
<td>hubif/hub_addr_4_s1/CLK</td>
</tr>
<tr>
<td>6.419</td>
<td>0.198</td>
<td>tC2Q</td>
<td>FR</td>
<td>8</td>
<td>R17C45[2][A]</td>
<td style=" font-weight:bold;">hubif/hub_addr_4_s1/Q</td>
</tr>
<tr>
<td>6.549</td>
<td>0.130</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C44[3][A]</td>
<td>hubif/n61_s1/I0</td>
</tr>
<tr>
<td>6.796</td>
<td>0.248</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R17C44[3][A]</td>
<td style=" background: #97FFFF;">hubif/n61_s1/F</td>
</tr>
<tr>
<td>6.796</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C44[3][A]</td>
<td style=" font-weight:bold;">hubif/hub_addr_5_s1/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clkn[0]</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>22</td>
<td>R21C44[0][A]</td>
<td>clkn_0_s0/Q</td>
</tr>
<tr>
<td>6.226</td>
<td>1.226</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C44[3][A]</td>
<td>hubif/hub_addr_5_s1/CLK</td>
</tr>
<tr>
<td>6.258</td>
<td>0.031</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R17C44[3][A]</td>
<td>hubif/hub_addr_5_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.005</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.221, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.248, 43.043%; route: 0.130, 22.609%; tC2Q: 0.198, 34.348%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.226, 100.000%</td>
</tr>
</table>
<h3>Path17</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.540</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.831</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.291</td>
</tr>
<tr>
<td class="label">From</td>
<td>frame_count_7_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>frame_count_7_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>frame_clk_Z:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>frame_clk_Z:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>frame_clk_Z</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>12</td>
<td>R21C45[2][A]</td>
<td>hubif/frame_clk_s1/Q</td>
</tr>
<tr>
<td>1.315</td>
<td>1.315</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C48[0][A]</td>
<td>frame_count_7_s0/CLK</td>
</tr>
<tr>
<td>1.491</td>
<td>0.176</td>
<td>tC2Q</td>
<td>RF</td>
<td>7</td>
<td>R18C48[0][A]</td>
<td style=" font-weight:bold;">frame_count_7_s0/Q</td>
</tr>
<tr>
<td>1.506</td>
<td>0.015</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R18C48[0][A]</td>
<td>n110_s/I1</td>
</tr>
<tr>
<td>1.831</td>
<td>0.325</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R18C48[0][A]</td>
<td style=" background: #97FFFF;">n110_s/SUM</td>
</tr>
<tr>
<td>1.831</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C48[0][A]</td>
<td style=" font-weight:bold;">frame_count_7_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>frame_clk_Z</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>12</td>
<td>R21C45[2][A]</td>
<td>hubif/frame_clk_s1/Q</td>
</tr>
<tr>
<td>1.315</td>
<td>1.315</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C48[0][A]</td>
<td>frame_count_7_s0/CLK</td>
</tr>
<tr>
<td>1.291</td>
<td>-0.024</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R18C48[0][A]</td>
<td>frame_count_7_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.315, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.325, 62.954%; route: 0.015, 2.906%; tC2Q: 0.176, 34.140%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.315, 100.000%</td>
</tr>
</table>
<h3>Path18</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.540</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.831</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.291</td>
</tr>
<tr>
<td class="label">From</td>
<td>frame_count_9_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>frame_count_9_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>frame_clk_Z:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>frame_clk_Z:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>frame_clk_Z</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>12</td>
<td>R21C45[2][A]</td>
<td>hubif/frame_clk_s1/Q</td>
</tr>
<tr>
<td>1.315</td>
<td>1.315</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C48[1][A]</td>
<td>frame_count_9_s0/CLK</td>
</tr>
<tr>
<td>1.491</td>
<td>0.176</td>
<td>tC2Q</td>
<td>RF</td>
<td>7</td>
<td>R18C48[1][A]</td>
<td style=" font-weight:bold;">frame_count_9_s0/Q</td>
</tr>
<tr>
<td>1.506</td>
<td>0.015</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R18C48[1][A]</td>
<td>n108_s/I1</td>
</tr>
<tr>
<td>1.831</td>
<td>0.325</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R18C48[1][A]</td>
<td style=" background: #97FFFF;">n108_s/SUM</td>
</tr>
<tr>
<td>1.831</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C48[1][A]</td>
<td style=" font-weight:bold;">frame_count_9_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>frame_clk_Z</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>12</td>
<td>R21C45[2][A]</td>
<td>hubif/frame_clk_s1/Q</td>
</tr>
<tr>
<td>1.315</td>
<td>1.315</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C48[1][A]</td>
<td>frame_count_9_s0/CLK</td>
</tr>
<tr>
<td>1.291</td>
<td>-0.024</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R18C48[1][A]</td>
<td>frame_count_9_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.315, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.325, 62.954%; route: 0.015, 2.906%; tC2Q: 0.176, 34.140%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.315, 100.000%</td>
</tr>
</table>
<h3>Path19</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.540</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>6.816</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>6.276</td>
</tr>
<tr>
<td class="label">From</td>
<td>hubif/hub_addr_3_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>hubif/hub_addr_3_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clkn[0]:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clkn[0]:[F]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clkn[0]</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>22</td>
<td>R21C44[0][A]</td>
<td>clkn_0_s0/Q</td>
</tr>
<tr>
<td>6.221</td>
<td>1.221</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C45[2][B]</td>
<td>hubif/hub_addr_3_s1/CLK</td>
</tr>
<tr>
<td>6.416</td>
<td>0.195</td>
<td>tC2Q</td>
<td>FF</td>
<td>6</td>
<td>R17C45[2][B]</td>
<td style=" font-weight:bold;">hubif/hub_addr_3_s1/Q</td>
</tr>
<tr>
<td>6.506</td>
<td>0.090</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C45[2][B]</td>
<td>hubif/n63_s1/I3</td>
</tr>
<tr>
<td>6.816</td>
<td>0.310</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R17C45[2][B]</td>
<td style=" background: #97FFFF;">hubif/n63_s1/F</td>
</tr>
<tr>
<td>6.816</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C45[2][B]</td>
<td style=" font-weight:bold;">hubif/hub_addr_3_s1/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clkn[0]</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>22</td>
<td>R21C44[0][A]</td>
<td>clkn_0_s0/Q</td>
</tr>
<tr>
<td>6.221</td>
<td>1.221</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C45[2][B]</td>
<td>hubif/hub_addr_3_s1/CLK</td>
</tr>
<tr>
<td>6.276</td>
<td>0.055</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R17C45[2][B]</td>
<td>hubif/hub_addr_3_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.221, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.310, 52.101%; route: 0.090, 15.126%; tC2Q: 0.195, 32.773%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.221, 100.000%</td>
</tr>
</table>
<h3>Path20</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.567</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.888</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.321</td>
</tr>
<tr>
<td class="label">From</td>
<td>frame_count_1_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>frame_count_1_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>frame_clk_Z:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>frame_clk_Z:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>frame_clk_Z</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>12</td>
<td>R21C45[2][A]</td>
<td>hubif/frame_clk_s1/Q</td>
</tr>
<tr>
<td>1.320</td>
<td>1.320</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C47[0][A]</td>
<td>frame_count_1_s0/CLK</td>
</tr>
<tr>
<td>1.496</td>
<td>0.176</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>R18C47[0][A]</td>
<td style=" font-weight:bold;">frame_count_1_s0/Q</td>
</tr>
<tr>
<td>1.578</td>
<td>0.082</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R18C47[0][A]</td>
<td>n116_s/I0</td>
</tr>
<tr>
<td>1.888</td>
<td>0.310</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R18C47[0][A]</td>
<td style=" background: #97FFFF;">n116_s/SUM</td>
</tr>
<tr>
<td>1.888</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C47[0][A]</td>
<td style=" font-weight:bold;">frame_count_1_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>frame_clk_Z</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>12</td>
<td>R21C45[2][A]</td>
<td>hubif/frame_clk_s1/Q</td>
</tr>
<tr>
<td>1.320</td>
<td>1.320</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C47[0][A]</td>
<td>frame_count_1_s0/CLK</td>
</tr>
<tr>
<td>1.321</td>
<td>0.001</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R18C47[0][A]</td>
<td>frame_count_1_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.320, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.310, 54.505%; route: 0.082, 14.505%; tC2Q: 0.176, 30.989%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.320, 100.000%</td>
</tr>
</table>
<h3>Path21</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.579</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.900</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.321</td>
</tr>
<tr>
<td class="label">From</td>
<td>frame_count_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>frame_count_5_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>frame_clk_Z:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>frame_clk_Z:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>frame_clk_Z</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>12</td>
<td>R21C45[2][A]</td>
<td>hubif/frame_clk_s1/Q</td>
</tr>
<tr>
<td>1.320</td>
<td>1.320</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C47[1][A]</td>
<td>frame_count_3_s0/CLK</td>
</tr>
<tr>
<td>1.496</td>
<td>0.176</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>R18C47[1][A]</td>
<td style=" font-weight:bold;">frame_count_3_s0/Q</td>
</tr>
<tr>
<td>1.500</td>
<td>0.004</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R18C47[1][A]</td>
<td>n114_s/I1</td>
</tr>
<tr>
<td>1.743</td>
<td>0.244</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R18C47[1][A]</td>
<td style=" background: #97FFFF;">n114_s/COUT</td>
</tr>
<tr>
<td>1.743</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R18C47[1][B]</td>
<td>n113_s/CIN</td>
</tr>
<tr>
<td>1.768</td>
<td>0.025</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R18C47[1][B]</td>
<td style=" background: #97FFFF;">n113_s/COUT</td>
</tr>
<tr>
<td>1.768</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R18C47[2][A]</td>
<td>n112_s/CIN</td>
</tr>
<tr>
<td>1.900</td>
<td>0.131</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R18C47[2][A]</td>
<td style=" background: #97FFFF;">n112_s/SUM</td>
</tr>
<tr>
<td>1.900</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C47[2][A]</td>
<td style=" font-weight:bold;">frame_count_5_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>frame_clk_Z</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>12</td>
<td>R21C45[2][A]</td>
<td>hubif/frame_clk_s1/Q</td>
</tr>
<tr>
<td>1.320</td>
<td>1.320</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C47[2][A]</td>
<td>frame_count_5_s0/CLK</td>
</tr>
<tr>
<td>1.321</td>
<td>0.001</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R18C47[2][A]</td>
<td>frame_count_5_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>3</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.320, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.400, 68.966%; route: 0.004, 0.647%; tC2Q: 0.176, 30.388%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.320, 100.000%</td>
</tr>
</table>
<h3>Path22</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.582</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.665</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.082</td>
</tr>
<tr>
<td class="label">From</td>
<td>reset_cnt_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>reset_cnt_4_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>CLK_IN:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>CLK_IN:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>CLK_IN</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>CLK_IN_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>8</td>
<td>IOB12[A]</td>
<td>CLK_IN_ibuf/O</td>
</tr>
<tr>
<td>1.081</td>
<td>0.406</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C46[1][A]</td>
<td>reset_cnt_2_s0/CLK</td>
</tr>
<tr>
<td>1.257</td>
<td>0.176</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R21C46[1][A]</td>
<td style=" font-weight:bold;">reset_cnt_2_s0/Q</td>
</tr>
<tr>
<td>1.265</td>
<td>0.008</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R21C46[1][A]</td>
<td>n12_s/I1</td>
</tr>
<tr>
<td>1.509</td>
<td>0.244</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R21C46[1][A]</td>
<td style=" background: #97FFFF;">n12_s/COUT</td>
</tr>
<tr>
<td>1.509</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R21C46[1][B]</td>
<td>n11_s/CIN</td>
</tr>
<tr>
<td>1.534</td>
<td>0.025</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R21C46[1][B]</td>
<td style=" background: #97FFFF;">n11_s/COUT</td>
</tr>
<tr>
<td>1.534</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R21C46[2][A]</td>
<td>n10_s/CIN</td>
</tr>
<tr>
<td>1.665</td>
<td>0.131</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R21C46[2][A]</td>
<td style=" background: #97FFFF;">n10_s/SUM</td>
</tr>
<tr>
<td>1.665</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C46[2][A]</td>
<td style=" font-weight:bold;">reset_cnt_4_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>CLK_IN</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>CLK_IN_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>8</td>
<td>IOB12[A]</td>
<td>CLK_IN_ibuf/O</td>
</tr>
<tr>
<td>1.081</td>
<td>0.406</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C46[2][A]</td>
<td>reset_cnt_4_s0/CLK</td>
</tr>
<tr>
<td>1.082</td>
<td>0.001</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R21C46[2][A]</td>
<td>reset_cnt_4_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>3</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 62.481%; route: 0.406, 37.519%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.400, 68.522%; route: 0.008, 1.285%; tC2Q: 0.176, 30.193%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 62.481%; route: 0.406, 37.519%</td>
</tr>
</table>
<h3>Path23</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.585</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.906</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.321</td>
</tr>
<tr>
<td class="label">From</td>
<td>frame_count_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>frame_count_4_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>frame_clk_Z:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>frame_clk_Z:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>frame_clk_Z</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>12</td>
<td>R21C45[2][A]</td>
<td>hubif/frame_clk_s1/Q</td>
</tr>
<tr>
<td>1.320</td>
<td>1.320</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C47[1][A]</td>
<td>frame_count_3_s0/CLK</td>
</tr>
<tr>
<td>1.496</td>
<td>0.176</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>R18C47[1][A]</td>
<td style=" font-weight:bold;">frame_count_3_s0/Q</td>
</tr>
<tr>
<td>1.500</td>
<td>0.004</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R18C47[1][A]</td>
<td>n114_s/I1</td>
</tr>
<tr>
<td>1.743</td>
<td>0.244</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R18C47[1][A]</td>
<td style=" background: #97FFFF;">n114_s/COUT</td>
</tr>
<tr>
<td>1.743</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R18C47[1][B]</td>
<td>n113_s/CIN</td>
</tr>
<tr>
<td>1.906</td>
<td>0.162</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R18C47[1][B]</td>
<td style=" background: #97FFFF;">n113_s/SUM</td>
</tr>
<tr>
<td>1.906</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C47[1][B]</td>
<td style=" font-weight:bold;">frame_count_4_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>frame_clk_Z</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>12</td>
<td>R21C45[2][A]</td>
<td>hubif/frame_clk_s1/Q</td>
</tr>
<tr>
<td>1.320</td>
<td>1.320</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C47[1][B]</td>
<td>frame_count_4_s0/CLK</td>
</tr>
<tr>
<td>1.321</td>
<td>0.001</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R18C47[1][B]</td>
<td>frame_count_4_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>3</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.320, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.406, 69.296%; route: 0.004, 0.640%; tC2Q: 0.176, 30.064%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.320, 100.000%</td>
</tr>
</table>
<h3>Path24</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.589</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.671</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.082</td>
</tr>
<tr>
<td class="label">From</td>
<td>reset_cnt_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>reset_cnt_3_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>CLK_IN:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>CLK_IN:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>CLK_IN</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>CLK_IN_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>8</td>
<td>IOB12[A]</td>
<td>CLK_IN_ibuf/O</td>
</tr>
<tr>
<td>1.081</td>
<td>0.406</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C46[1][A]</td>
<td>reset_cnt_2_s0/CLK</td>
</tr>
<tr>
<td>1.257</td>
<td>0.176</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R21C46[1][A]</td>
<td style=" font-weight:bold;">reset_cnt_2_s0/Q</td>
</tr>
<tr>
<td>1.265</td>
<td>0.008</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R21C46[1][A]</td>
<td>n12_s/I1</td>
</tr>
<tr>
<td>1.509</td>
<td>0.244</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R21C46[1][A]</td>
<td style=" background: #97FFFF;">n12_s/COUT</td>
</tr>
<tr>
<td>1.509</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R21C46[1][B]</td>
<td>n11_s/CIN</td>
</tr>
<tr>
<td>1.671</td>
<td>0.162</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R21C46[1][B]</td>
<td style=" background: #97FFFF;">n11_s/SUM</td>
</tr>
<tr>
<td>1.671</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C46[1][B]</td>
<td style=" font-weight:bold;">reset_cnt_3_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>CLK_IN</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>CLK_IN_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>8</td>
<td>IOB12[A]</td>
<td>CLK_IN_ibuf/O</td>
</tr>
<tr>
<td>1.081</td>
<td>0.406</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C46[1][B]</td>
<td>reset_cnt_3_s0/CLK</td>
</tr>
<tr>
<td>1.082</td>
<td>0.001</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R21C46[1][B]</td>
<td>reset_cnt_3_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>3</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 62.481%; route: 0.406, 37.519%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.406, 68.856%; route: 0.008, 1.271%; tC2Q: 0.176, 29.873%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 62.481%; route: 0.406, 37.519%</td>
</tr>
</table>
<h3>Path25</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.596</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.912</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.316</td>
</tr>
<tr>
<td class="label">From</td>
<td>frame_count_7_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>frame_count_8_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>frame_clk_Z:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>frame_clk_Z:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>frame_clk_Z</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>12</td>
<td>R21C45[2][A]</td>
<td>hubif/frame_clk_s1/Q</td>
</tr>
<tr>
<td>1.315</td>
<td>1.315</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C48[0][A]</td>
<td>frame_count_7_s0/CLK</td>
</tr>
<tr>
<td>1.491</td>
<td>0.176</td>
<td>tC2Q</td>
<td>RF</td>
<td>7</td>
<td>R18C48[0][A]</td>
<td style=" font-weight:bold;">frame_count_7_s0/Q</td>
</tr>
<tr>
<td>1.506</td>
<td>0.015</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R18C48[0][A]</td>
<td>n110_s/I1</td>
</tr>
<tr>
<td>1.750</td>
<td>0.244</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R18C48[0][A]</td>
<td style=" background: #97FFFF;">n110_s/COUT</td>
</tr>
<tr>
<td>1.750</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R18C48[0][B]</td>
<td>n109_s/CIN</td>
</tr>
<tr>
<td>1.912</td>
<td>0.162</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R18C48[0][B]</td>
<td style=" background: #97FFFF;">n109_s/SUM</td>
</tr>
<tr>
<td>1.912</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C48[0][B]</td>
<td style=" font-weight:bold;">frame_count_8_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>frame_clk_Z</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>12</td>
<td>R21C45[2][A]</td>
<td>hubif/frame_clk_s1/Q</td>
</tr>
<tr>
<td>1.315</td>
<td>1.315</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C48[0][B]</td>
<td>frame_count_8_s0/CLK</td>
</tr>
<tr>
<td>1.316</td>
<td>0.001</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R18C48[0][B]</td>
<td>frame_count_8_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>3</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.315, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.406, 67.992%; route: 0.015, 2.510%; tC2Q: 0.176, 29.498%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.315, 100.000%</td>
</tr>
</table>
<h3><a name="Recovery_Analysis">Recovery Analysis Report</a></h3>
<h4>Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1</h4>
<h4>No recovery paths to report!</h4>
<h3><a name="Removal_Analysis">Removal Analysis Report</a></h3>
<h4>Report Command:report_timing -removal -max_paths 25 -max_common_paths 1</h4>
<h4>No removal paths to report!</h4>
<h2><a name="Minimum_Pulse_Width_Report">Minimum Pulse Width Report:</a></h2>
<h4>Report Command:report_min_pulse_width -nworst 10 -detail</h4>
<h3>MPW1</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>3.042</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>4.042</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>High Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>clkn[0]</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>logo_rom/prom_inst_1</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>clkn[0]</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>clkn_0_s0/Q</td>
</tr>
<tr>
<td>2.190</td>
<td>2.190</td>
<td>tNET</td>
<td>RR</td>
<td>logo_rom/prom_inst_1/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>clkn[0]</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>clkn_0_s0/Q</td>
</tr>
<tr>
<td>6.232</td>
<td>1.232</td>
<td>tNET</td>
<td>FF</td>
<td>logo_rom/prom_inst_1/CLK</td>
</tr>
</table>
<h3>MPW2</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>3.042</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>4.042</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>High Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>clkn[0]</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>logo_rom/prom_inst_2</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>clkn[0]</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>clkn_0_s0/Q</td>
</tr>
<tr>
<td>2.190</td>
<td>2.190</td>
<td>tNET</td>
<td>RR</td>
<td>logo_rom/prom_inst_2/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>clkn[0]</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>clkn_0_s0/Q</td>
</tr>
<tr>
<td>6.232</td>
<td>1.232</td>
<td>tNET</td>
<td>FF</td>
<td>logo_rom/prom_inst_2/CLK</td>
</tr>
</table>
<h3>MPW3</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>3.047</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>4.047</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>High Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>clkn[0]</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>logo_rom/prom_inst_0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>clkn[0]</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>clkn_0_s0/Q</td>
</tr>
<tr>
<td>2.180</td>
<td>2.180</td>
<td>tNET</td>
<td>RR</td>
<td>logo_rom/prom_inst_0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>clkn[0]</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>clkn_0_s0/Q</td>
</tr>
<tr>
<td>6.227</td>
<td>1.227</td>
<td>tNET</td>
<td>FF</td>
<td>logo_rom/prom_inst_0/CLK</td>
</tr>
</table>
<h3>MPW4</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>3.047</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>4.047</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>High Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>clkn[0]</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>logo_rom/prom_inst_3</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>clkn[0]</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>clkn_0_s0/Q</td>
</tr>
<tr>
<td>2.180</td>
<td>2.180</td>
<td>tNET</td>
<td>RR</td>
<td>logo_rom/prom_inst_3/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>clkn[0]</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>clkn_0_s0/Q</td>
</tr>
<tr>
<td>6.227</td>
<td>1.227</td>
<td>tNET</td>
<td>FF</td>
<td>logo_rom/prom_inst_3/CLK</td>
</tr>
</table>
<h3>MPW5</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>3.100</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>4.100</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>clkn[0]</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>logo_rom/prom_inst_1</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>clkn[0]</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>clkn_0_s0/Q</td>
</tr>
<tr>
<td>7.063</td>
<td>2.063</td>
<td>tNET</td>
<td>FF</td>
<td>logo_rom/prom_inst_1/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>clkn[0]</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>clkn_0_s0/Q</td>
</tr>
<tr>
<td>11.164</td>
<td>1.164</td>
<td>tNET</td>
<td>RR</td>
<td>logo_rom/prom_inst_1/CLK</td>
</tr>
</table>
<h3>MPW6</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>3.100</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>4.100</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>clkn[0]</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>logo_rom/prom_inst_2</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>clkn[0]</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>clkn_0_s0/Q</td>
</tr>
<tr>
<td>7.063</td>
<td>2.063</td>
<td>tNET</td>
<td>FF</td>
<td>logo_rom/prom_inst_2/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>clkn[0]</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>clkn_0_s0/Q</td>
</tr>
<tr>
<td>11.164</td>
<td>1.164</td>
<td>tNET</td>
<td>RR</td>
<td>logo_rom/prom_inst_2/CLK</td>
</tr>
</table>
<h3>MPW7</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>3.105</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>4.105</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>clkn[0]</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>logo_rom/prom_inst_3</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>clkn[0]</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>clkn_0_s0/Q</td>
</tr>
<tr>
<td>7.054</td>
<td>2.054</td>
<td>tNET</td>
<td>FF</td>
<td>logo_rom/prom_inst_3/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>clkn[0]</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>clkn_0_s0/Q</td>
</tr>
<tr>
<td>11.159</td>
<td>1.159</td>
<td>tNET</td>
<td>RR</td>
<td>logo_rom/prom_inst_3/CLK</td>
</tr>
</table>
<h3>MPW8</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>3.105</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>4.105</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>clkn[0]</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>logo_rom/prom_inst_0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>clkn[0]</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>clkn_0_s0/Q</td>
</tr>
<tr>
<td>7.054</td>
<td>2.054</td>
<td>tNET</td>
<td>FF</td>
<td>logo_rom/prom_inst_0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>clkn[0]</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>clkn_0_s0/Q</td>
</tr>
<tr>
<td>11.159</td>
<td>1.159</td>
<td>tNET</td>
<td>RR</td>
<td>logo_rom/prom_inst_0/CLK</td>
</tr>
</table>
<h3>MPW9</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>3.751</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>4.001</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>0.250</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>High Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>frame_clk_Z</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>frame_count_0_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>frame_clk_Z</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>hubif/frame_clk_s1/Q</td>
</tr>
<tr>
<td>2.436</td>
<td>2.436</td>
<td>tNET</td>
<td>RR</td>
<td>frame_count_0_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>frame_clk_Z</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>hubif/frame_clk_s1/Q</td>
</tr>
<tr>
<td>6.436</td>
<td>1.436</td>
<td>tNET</td>
<td>FF</td>
<td>frame_count_0_s0/CLK</td>
</tr>
</table>
<h3>MPW10</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>3.756</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>4.006</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>0.250</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>High Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>frame_clk_Z</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>frame_count_5_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>frame_clk_Z</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>hubif/frame_clk_s1/Q</td>
</tr>
<tr>
<td>2.404</td>
<td>2.404</td>
<td>tNET</td>
<td>RR</td>
<td>frame_count_5_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>frame_clk_Z</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>hubif/frame_clk_s1/Q</td>
</tr>
<tr>
<td>6.409</td>
<td>1.409</td>
<td>tNET</td>
<td>FF</td>
<td>frame_count_5_s0/CLK</td>
</tr>
</table>
<h2><a name="High_Fanout_Nets_Report">High Fanout Nets Report:</a></h2>
<h4>Report Command:report_high_fanout_nets -max_nets 10</h4>
<table class="detail_table">
<tr>
<th class="label">FANOUT</th>
<th class="label">NET NAME</th>
<th class="label">WORST SLACK</th>
<th class="label">MAX DELAY</th>
</tr>
<tr>
<td>22</td>
<td>n106_5</td>
<td>-2.322</td>
<td>2.614</td>
</tr>
<tr>
<td>22</td>
<td>clkn[0]</td>
<td>6.212</td>
<td>2.409</td>
</tr>
<tr>
<td>12</td>
<td>frame_clk_Z</td>
<td>7.689</td>
<td>2.586</td>
</tr>
<tr>
<td>12</td>
<td>ram_raddr[6]</td>
<td>1.819</td>
<td>2.964</td>
</tr>
<tr>
<td>11</td>
<td>state[0]</td>
<td>5.805</td>
<td>1.081</td>
</tr>
<tr>
<td>10</td>
<td>ram_raddr[7]</td>
<td>1.484</td>
<td>3.196</td>
</tr>
<tr>
<td>10</td>
<td>ram_raddr[8]</td>
<td>0.870</td>
<td>3.774</td>
</tr>
<tr>
<td>9</td>
<td>ram_raddr[0]</td>
<td>2.214</td>
<td>2.420</td>
</tr>
<tr>
<td>8</td>
<td>ram_raddr[4]</td>
<td>2.596</td>
<td>2.075</td>
</tr>
<tr>
<td>8</td>
<td>ram_raddr[9]</td>
<td>1.294</td>
<td>3.386</td>
</tr>
</table>
<h2><a name="Route_Congestions_Report">Route Congestions Report:</a></h2>
<h4>Report Command:report_route_congestion -max_grids 10</h4>
<table class="detail_table">
<tr>
<th class="label">GRID LOC</th>
<th class="label">ROUTE CONGESTIONS</th>
</tr>
<tr>
<td>R17C45</td>
<td>33.33%</td>
</tr>
<tr>
<td>R18C47</td>
<td>25.00%</td>
</tr>
<tr>
<td>R21C46</td>
<td>25.00%</td>
</tr>
<tr>
<td>R18C45</td>
<td>22.22%</td>
</tr>
<tr>
<td>R18C48</td>
<td>20.83%</td>
</tr>
<tr>
<td>R10C47</td>
<td>19.44%</td>
</tr>
<tr>
<td>R10C50</td>
<td>19.44%</td>
</tr>
<tr>
<td>R21C45</td>
<td>18.06%</td>
</tr>
<tr>
<td>R19C45</td>
<td>18.06%</td>
</tr>
<tr>
<td>R18C49</td>
<td>18.06%</td>
</tr>
</table>
<h2><a name="Timing_Exceptions_Report">Timing Exceptions Report:</a></h2>
<h3><a name="Setup_Analysis_Exceptions">Setup Analysis Report</a></h3>
<h4>Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h3><a name="Hold_Analysis_Exceptions">Hold Analysis Report</a></h3>
<h4>Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h3><a name="Recovery_Analysis_Exceptions">Recovery Analysis Report</a></h3>
<h4>Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h3><a name="Removal_Analysis_Exceptions">Removal Analysis Report</a></h3>
<h4>Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h2><a name="SDC_Report">Timing Constraints Report:</a></h2>
<table class="detail_table">
<tr>
<th class="label">SDC Command Type</th>
<th class="label">State</th>
<th class="label">Detail Command</th>
</tr>
</table>
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